I2S Digital Audio Diagram - Teli LE910C1-NA Design Manual

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LE910Cx HW User Guide
Parameter
t(auxsync)
AUX_PCM__SYNC cycle time
t(auxsynca)
AUX_PCM_SYNC asserted time
t(auxsyncd)
AUX_PCM_SYNC de-asserted time
t(auxclk)
AUX_PCM_CLK cycle time
t(auxclkh)
AUX_PCM_CLK high time
t(auxclkl)
AUX_PCM_CLK low time
AUX_PCM_SYNC setup time to
t(suauxsync)
AUX_PCM_CLK rising
PCM_DIN hold time after
t(hauxsync)
AUX_PCM_CLK rising
AUX_PCM_DIN setup time to
t(suauxdin)
AUX_PCM_CLK falling
AUX_ PCM_DIN hold time after
t(hauxdin)
AUX_PCM_CLK falling
Delay from AUX_PCM_CLK to
t(pauxdout)
AUX_PCM_DOUT valid
Table 35: AUX_PCM_CODEC Timing Parameters

8.6.1.3. I2S Digital Audio Diagram

1VV0301298 Rev. 33
Comments
Page 81 of 128
Not Subject to NDA
Min
Typ
Max
-
125
-
62.4
62.5
-
62.4
62.5
-
-
7.8
-
3.8
3.9
-
3.8
3.9
-
1.95
-
-
1.95
-
-
70
-
-
20
-
-
-
-
50
Unit
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
2021-06-29

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