Schematic Diagram Of The External Cs1/Cs2 Memory Interface - Motorola DSP56852 User Manual

This memory bank will operate with one wait state access while the DSP56852 is running
at 120MHz and can be disabled by removing the jumpers at JG1.
Figure 2-2. Schematic Diagram of the External CS1/CS2 Memory Interface
2-4
Freescale Semiconductor, Inc.
DSP56852
A0-A16
D0-D15
RD
WR
CS1
CS2
Jumper Pin 1-2:
Enable SRAM Low Byte
Jumper Pin 3-4:
Enable SRAM High Byte
DSP56852EVM User's Manual
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GS72116
A0-A16
DQ0-DQ15
OE
WE
JG1
LB
1 2
HB
4
3
CE
MOTOROLA