Hisense PDP4220EU Service Manual page 24

5
SHEET 3
D
03. Graphic Inputs
SHEET 4
04. Video Decoder
C
DEC1Y[7..0]
DEC1CLK
DEC1HS
DEC1VS
DEC1ODD
SCFB1
SCR1
SCG1
SCB1
VOUT1
SHEET 9
B
09.PIP Video
SHEET12
DEC1HS
DEC1VS
A
VOUT1
SCB1
SCG1
SCR1
SCFB1
12.TELETEXT
5
4
SHEET 5
RXC+
RXC+ RXC+
RXC-
RXC- RXC-
RX2+
RX2+ RX2+
RX2-
RX2- RX2-
RX1+
RX1+ RX1+
RX1-
RX1- RX1-
RX0+
RX0+ RX0+
RX0-
RX0- RX0-
RED+
RED+ RED+
RED-
RED- RED-
GREEN+
GREEN+ GREEN+
GREEN-
GREEN- GREEN-
BLUE+
BLUE+ BLUE+
BLUE-
BLUE- BLUE-
SOG
SOG SOG
AHS
AHS AHS
AVS
AVS AVS
DVI_SCL
DVI_SCL DVI_SCL
DVI_SDA
DVI_SDA DVI_SDA
VGA_SCL
VGA_SCL VGA_SCL
VGA_SDA
VGA_SDA VGA_SDA
VGA_CAB
VGA_CAB VGA_CAB
DVI_CAB
DVI_CAB DVI_CAB
HD_SEL
HD_SEL HD_SEL
YPBPR_SEL
YPBPR_SEL YPBPR_SEL
VOLUME
VOLUME VOLUME
IO_MUTE
IO_MUTE IO_MUTE
IO_STBY
IO_STBY IO_STBY
ADC_IN2
ADC_IN2 ADC_IN2
PCRXD
PCRXD PCRXD
PCTXD
PCTXD PCTXD
TEXT_SEL
TEXT_SEL TEXT_SEL
SEC_SDA
SEC_SCL
MSTR_SDA
MSTR_SDA MSTR_SDA
MSTR_SCL
MSTR_SCL MSTR_SCL
/DEC_RESET
/DEC_RESET /DEC_RESET
CC_INT1
CC_INT1 CC_INT1
DEC2Y[7..0]
DEC2Y[7..0] DEC2Y[7..0]
DEC2HS
DEC2HS DEC2HS
DEC2ODD
DEC2ODD DEC2ODD
DEC2VS
DEC2VS DEC2VS
DEC2CLK
DEC2CLK DEC2CLK
DEC2DV
DEC2DV DEC2DV
MSTR_SDA
MSTR_SCL
ADC_IN1
ADC_IN1 ADC_IN1
/DEC_RESET
/DEC_RESET
CC_INT2
CC_INT2 CC_INT2
05. gm1601
DEC1CLK
DEC1Y[7..0]
SEC_SDA
SEC_SCL
MSTR_SDA
MSTR_SCL
4
3
SHEET 8
PS_ON PS_ON
SHEET11
ALARM
ALARM ALARM
DEBLU[7..0]
DEBLU[7..0] DEBLU[7..0]
DEGRN[7..0]
DEGRN[7..0] DEGRN[7..0]
DERED[7..0]
DERED[7..0] DERED[7..0]
LE
LE LE
PLE
PLE PLE
Hsync
Hsync Hsync
Vsync
Vsync Vsync
BLKH
BLKH BLKH
ADCK
ADCK ADCK
/LVDS_EN
/LVDS_EN /LVDS_EN
r0
r0 r0
r1
r1 r1
b0
b0 b0
b1
b1 b1
g0
g0 g0
g1
g1 g1
11.DS90C387
SHEET10
G/Y_OUT[7..0]
G/Y_OUT[7..0] G/Y_OUT[7..0]
R/V_OUT[7..0]
R/V_OUT[7..0] R/V_OUT[7..0]
B/U_OUT[7..0]
B/U_OUT[7..0] B/U_OUT[7..0]
VHS
VHS VHS
VVS
VVS VVS
VCLK
VCLK VCLK
VHREF
VHREF VHREF
/23RESET
/23RESET /23RESET
2300OE#
2300OE# 2300OE#
10.FLI2300
SHEET 6
FSDATA[0..31]
FSDATA[0..31] FSDATA[0..31]
FSADDR[0..11]
FSADDR[0..11] FSADDR[0..11]
FSCLK+
FSCLK+ FSCLK+
FSCLK-
FSCLK- FSCLK-
FSDQS
FSDQS FSDQS
FSCKE
FSCKE FSCKE
/FSRAS
/FSRAS /FSRAS
/FSCAS
/FSCAS /FSCAS
/FSWE
/FSWE /FSWE
FSBKSEL0
FSBKSEL0 FSBKSEL0
FSBKSEL1
FSBKSEL1 FSBKSEL1
FSDQM[0..3]
FSDQM[0..3] FSDQM[0..3]
06. Frame Store
OCMDATA[0..7]
OCMDATA[0..7]
OCMADDR[0..19]
OCMADDR[0..19]
/OCM_WE
/OCM_WE
/OCM_RE
/OCM_RE
/ROM_CS
/ROM_CS
24
3
2
08. Power
SEC_SDA
SEC_SCL
Genesis Microchip Inc. Genesis Microchip Inc. Genesis Microchip Inc.
Title Title Title
02. Top Level 02. Top Level 02. Top Level
Size Size Size Document Number Document Number Document Number
B B B B0114-SCH-01 B0114-SCH-01 B0114-SCH-01
Date: Date: Date: Monday, December 06, 2004 Monday, December 06, 2004 Monday, December 06, 2004
2
1
D
C
B
SHEET 7
OCMDATA[0..7]
OCMADDR[0..19]
/OCM_WE
/OCM_RE
/ROM_CS
07. Memory I/F
A
Rev Rev Rev
C C C
Sheet Sheet Sheet 2 2 2 of of of 10 10 10
1