Hisense PDP4220EU Service Manual page 29

5
D
OCMADDR[0..19]
5 OCMADDR[0..19]
OCMDATA[0..7]
5 OCMDATA[0..7]
/OCM_WE
5 /OCM_WE
/OCM_RE
5 /OCM_RE
/OCM_CS
5 /ROM_CS
C
B
RP720 10KX4 RP720 10KX4
OCMADDR8
1 8
OCMADDR9
2 7
OCMADDR10
3 6
OCMADDR12
4 5
OCMADDR11
1 8
OCMADDR13
2 7
OCMADDR14
3 6
OCMADDR15
4 5
OCMADDR16 RP721 10KX4 RP721 10KX4 INT_OSC
OCMADDR18
A 8-BIT_FLASH2
OCMADDR17 R700 R700 10K 10K 8-BIT_FLASH1
OCMADDR19 R701 R701 10K 10K
8-BIT_FLASH3
5
4
+3.3V_DIG
C700 C700 C701 C701
47uF 47uF 0.1uF 0.1uF
GND
+3.3V_DIG
RP723 RP723
RP722 RP722
10KX4 10KX4
10KX4 10KX4
10: LOW (Use TCLK)
11: LOW (set all display output to '0')
12: LOW
13: LOW(disable serial interface debug)
14: LOW
15: LOW
16: HIGH (use crystal)
17: LOW (8bit bus with OCM access external ROM)
18: HIGH
19: LOW
Custom1
Custom2
Serial_Interface_Debug1
TCLK Serial_Interface_Debug2
OUTPUTS_ZERO Serial_Interface_Debug3
OUTPUTS_ZERO
BOOTSTRAP HEADER
OPEN=1
SHUNTED=0
GND GND
4
3
/RESET
/RESET
R708 R708
4k7 4k7
EMPTY
R702 R702 0R 0R
R703 R703 0R 0R
R704 R704 0R 0R
R705 R705 EMPTY 0R 0R
R706 R706 0R 0R
EMPTY
GND
28
3
2
XU701 XU701
OCMDATA0
29
DQ0
OCMADDR1 OCMDATA1
25 31
A0 DQ1
OCMADDR2 OCMDATA2
24 33
A1 DQ2
OCMADDR3 OCMDATA3
23 35
A2 DQ3
OCMADDR4 OCMDATA4
22 38
A3 DQ4
OCMADDR5 OCMDATA5
21 40
A4 DQ5
OCMADDR6 OCMDATA6
20 42
A5 DQ6
OCMADDR7 OCMDATA7
19 44
A6 DQ7
OCMADDR8
18 30
A7 DQ8
OCMADDR9
8 32
A8 DQ9
OCMADDR10
7 34
A9 DQ10
OCMADDR11
6 36
A10 DQ11
OCMADDR12
5 39
A11 DQ12
OCMADDR13
4 41
A12 DQ13
OCMADDR14
3 43
A13 DQ14
OCMADDR15 OCMADDR0
2 45
A14 DQ15
OCMADDR16
1
A15
OCMADDR17
48 9
A16 NC
OCMADDR18
17 10
A17 NC
OCMADDR19
16 13
A18 NC
14
/WP
/ROM_CS
26 15
CE# RY/BY#
/OCM_RE +3.3V_DIG
28
OE#
/OCM_WE
11 37
WE# VCC
/RESET_FLH
12
RESET#
47 27
BYTE# VSS
R709 R709
46
VSS
10k 10k
29lv800b 29lv800b
GND GND
GND
R1 R1 R2 R2 R3 R3
10k 10k 10k 10k 10k 10k
Genesis Microchip Inc. Genesis Microchip Inc. Genesis Microchip Inc.
Title Title Title
07. Memory I/F 07. Memory I/F 07. Memory I/F
Size Size Size Document Number Document Number Document Number
B B B B0114-SCH-01 B0114-SCH-01 B0114-SCH-01
Date: Date: Date: Friday, November 04, 2005 Friday, November 04, 2005 Friday, November 04, 2005
2
1
D
R707 R707
4k7 4k7
EMPTY
C
GND
R4 R4
10k 10k
B
A
Rev Rev Rev
C C C
Sheet Sheet Sheet 7 7 7 of of of 10 10 10
1