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tc. After then the signal transforms to from 31～40pin digital YUV signal（4:2:2）(ITU-R656
format )and sends to PW1235 to DEINTERLACE etc。
3.1.1 .5 DVI digital signal disposal：
We use DVI-D interface 。
DVI digital signal（4channels DS signal）from DVI jack each send to 90、91、85、86、
80、81、93、94pin of SiI161B. By the control of 100、3pin (input bus)，after in SiI161B(VCR、
data resume、sync. Head test 、 enlarge circuit、decode circuit and logic interface circuit)，it
outputs digital R G B signal， which has two mode： one mode when 4 pin of SiI161B is low，
it output 24bit even pixel， when 4pin is high， it output 48biteven and odd pixel data， we connect
4pin to ground，so each signal from 10～17、20～27、30～37pin outputs R,G,B even pixel data，
switch with 24bit VGA digital signal disposalled by MST9885，and send to PW113 to transform
format，for sure ,the choice is control by PW113。
DVI interface 6、7pin is DDC data channel ，U7（24LC21A）is an E
some DVI data parameter information ， it connect to DDC data channel by bus， at the moment of
power on ，the status information is sent to host to identify，after identify，according to E
information outputs digital signal correctly。
VGA signal、video signal、DVI signal after digital disposal，sends to video format disposal
ic PW113 to change the video format ， outputs the digital R,G,B signal which fits PDP
display driver。
PW113 the input video signal after disposalled by PW113， outputs 852×480 resolution digital
R,G,B signal which fits PDP panel spec and relevant sync、clock signal and transform them into
LVDS by DS90CF383，send to PDP panel to control the panel display correctly。
29
2
ROM，which stores
2
ROM
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