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7、DVI Digital Receiver SiI161B
2.2.
General：
The Sil161B receiver uses Panel Link Digital technology to support high-resolution
displays up to UXGA. The Sil161B receiver supports up to true color panels (24 bit/pixel,
16.7M colors) in 1 or 2 pixels/clock mode. In addition, the receiver data output is time
staggered to reduce ground bounce that affects EMI. All Panel Link products are
designed on a scaleable CMOS architecture. This ensures support for future
performance requirements while maintaining the same logical interface. With this
scalable architecture, system designers can be assured that the interface will be fixed
through a number of technology and performance generations.
Pin Function Descriptions：
Pin(s)
90
RX0+
91
RX0-
85
RX1+
86
RX1-
80
RX2+
81
RX2-
93
RXC+
94
RXC-
49～56
QO0～QO7
59～66
QO8～QO15
69～75,77
QO16～QO23
10～17
QE0～QE7
20～27
QE8～QE15
30～37
QE16～QE23
99
RESERVED
100
OCK_INV
1
HS_DJTR
2
PD
3
ST
4
PIXS
7
STAG_OUT
Name
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input data pairs
TMDS Low Voltage Differential Signal input clock pair.
TMDS Low Voltage Differential Signal input clock pair.
8bit odd-pixel Blue output
8bit even-pixel Green output
8bit odd-pixel Red output
8bit even -pixel Blue output
8bit even -pixel Green output
8bit even -pixel Red output
Must be tied HIGH for normal operation.
ODCK Polarity. A LOW level selects normal ODCK
output. A HIGH level selects inverted ODCK output.
This pin enables/disable the HSYNC dejitter function.
To enable the HSYNC function this pin should be tied
high. To
Power Down (active LOW). A HIGH level indicates
normal operation. A LOW level indicates power down
mode.
Output Drive. A HIGH level selects HIGH output drive
strength. A LOW level selects LOW output drive
strength.
Pixel Select. A LOW level indicates one pixel (up to
24-bits) per clock mode using QE[23:0]. A HIGH level
indicates two pixels (up to 48-bits) per clock mode
using QE [23:0] for first pixel and QO[23:0] for second
pixel.
Staggered Output. A HIGH level selects normal
simultaneous outputs on all odd and even data lines.
Function
24
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