Lvds Backlight And Lvds Vdd (Jp1); Digital Io And Address (Jp2); Serial Port Configuration (Jp3) - Diamond Systems SATURN SAT-E3940-4GA Manual

8.1 LVDS Backlight and LVDS VDD (JP1)

Jumper block JP1 configures the voltage supply for the LCD backlight and LVDS VDD.
By default, LVDS backlight is provided with +12V and the LVDS VDD is provided with 3.3V.
Position
12V*
5V
x
5V
3V3*
*Default Mode

8.2 Digital IO and Address (JP2)

Jumper block JP2 configures the Voltage level for Digital IO and Pull up/down. It also selects the base address for
Data acquisition FPGA.
By default, Digital IO is 3.3V and pulled down. FPGA base address is set to 0x280 and USB3.0/2.0 Port 0 is Host
by default.
Position
ID
ADDR
PD
PU
3V3
5V
*Default Mode

8.3 Serial Port Configuration (JP3)

Jumper block JP3 configures Serial Port1-2 protocol and termination select during RS422/485 mode.
By default, Serial ports are set to Internal loopback mode and terminations are disabled. The protocol selection is
superseded by DAQ software setting.
Position
SC1
SC0
RX2
TX2
RX1
TX1
*Default Mode
Saturn User Manual V1
Function
LCD Backlight Voltage
LCD Backlight Voltage
-
LCD VDD Voltage
LCD VDD Voltage
Function
USB3.0/2.0 Port0 Mode
FPGA Base Address
DIO Pull Down Enable
DIO Pull Up Enable
DIO Voltage Level
DIO Voltage Level
Function
Ser Port1-2 Mode select1
Ser Port1-2 Mode select0
Serial Port2 RX Termination
Serial Port2 TX Termination
Serial Port1 RX Termination
Serial Port1 TX Termination
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IN OUT
12V -
5V -
- -
5V -
3.3V -
IN OUT
Host Device
0x240 0x280
Enabled Disabled
Enabled Disabled
3.3V -
5V -
IN OUT
Refer Table Below -
Refer Table Below
Enabled Disabled
Enabled Disabled
Enabled Disabled
Enabled Disabled
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