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Diamond Systems ELEKTRA FD-64 User Manual

High integration cpu with ethernet and data acquisition
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ELEKTRA™
High Integration CPU
with Ethernet and Data Acquisition
User Manual Revision 1.01
Document # 7650530
Copyright © 2005
Diamond Systems Corporation
8430-D Central Ave.
Newark, CA 94560
Tel (510) 456-7800
www.diamondsystems.com

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Summary of Contents for Diamond Systems ELEKTRA FD-64

  • Page 1 ELEKTRA™ High Integration CPU with Ethernet and Data Acquisition User Manual Revision 1.01 Document # 7650530 Copyright © 2005 Diamond Systems Corporation 8430-D Central Ave. Newark, CA 94560 Tel (510) 456-7800 www.diamondsystems.com...

  • Page 2: Table Of Contents

    ELEKTRA High-Performance Rugged Embedded CPU with Data Acquisition TABLE OF CONTENTS ..........................5 ESCRIPTION ............................6 EATURES ELEKTRA B ......................9 OARD RAWING I/O H ............................. 10 EADERS PC/104 Bus Connectors ......................10 Main I/O Connector – J3......................11 Input Power – J11 ..........................14 Output Power –...
  • Page 3 12.3 Wait for analog input circuit to settle..................58 12.4 Perform an A/D conversion on the current channel..............59 12.5 Wait for the conversion to finish ....................59 12.6 Read the data from the board....................59 12.7 Convert the numerical data to a meaningful value ..............60 A/D S FIFO O ................
  • Page 4 Table 4: J12 – Output Power Connector Pinout ................15 Table 5: J4 – Ethernet Connector Pinout ..................15 Table 6: J5 – USB Connector Pinout....................15 Table 7: J6 – Watchdog Connector Pinout..................17 Table 8: J8 – IDE Drive Connector Pinout..................17 Table 9: J14 – Data Acqisition Connector Pinout ................18 Table 10: J15 –...

  • Page 5: Description

    Only the ISA bus is brought out to expansion connectors for the connection of add-on boards. Diamond Systems manufactures a wide variety of compatible PC/104 add-on board for analog I/O, digital I/O, counter/timer functions, serial ports, and power supply.

  • Page 6: Features

    2. FEATURES Processor Section ♦ STPC Vega processor running at 200MHz ♦ Pentium II class platform with MMX including SDRAM, IDE controller and USB Core System ♦ 128MB SDRAM system memory (standard) ♦ 100MHz memory bus ♦ 2MB 16-bit wide integrated flash memory for BIOS and user programs ♦...
  • Page 7 Data Acquisition Subsystem Analog Input ♦ 16 single-ended / 8 differential inputs, 16-bit resolution ♦ 100KHz maximum aggregate A/D sampling rate ♦ Programmable input ranges/gains: +/-10V, +/-5V, +/-2.5V, +/-1.25V, 0-10V, 0-5V, 0-2.5V ♦ 5 ppm/ C typical drift accuracy when using auto calibration. Not more than +/-10ppm/oC worse case drift accuracy when using auto calibration across the specified temperature range.
  • Page 8 Digital I/O ♦ 24 programmable digital I/O, 3.3V and 5V logic compatible ♦ Input voltage Logic 0: -0.5V min, 0.8V max ♦ Logic 1: 2.0V min, 5.5V max ♦ Input current ±3µA max ♦ Output voltage Logic 0: 0.0V min, 0.4V max ♦...

  • Page 9: Elektra Board Drawing

    3. ELEKTRA BOARD DRAWING I/O Connectors PC/104 8-bit bus connector PC/104 16-bit bus connector Main user I/O connector Ethernet port Dual USB ports Watchdog/Failsafe Features IDE drive connector External battery connector Jumper Block Input power connector Switched output power connector Data acquisition I/O connector Auxiliary serial port connector J17 Autocal connector...

  • Page 10: I/O Headers

    4. I/O HEADERS All cables mentioned in this chapter are included in Diamond Systems’ cable kit C-ELK-KIT. These cables are further described in chapter 23. Some cables are also available individually. 4.1 PC/104 Bus Connectors The PC/104 bus is essentially identical to the ISA Bus except for the physical design. It specifies two pin and socket connectors for the bus signals.

  • Page 11: Main I/O Connector - J3

    Infra Red Power and HDD LEDs This connector mates with Diamond Systems’ cable no. C-PRZ-01, which consists of a dual- ribbon-cable assembly with industry-standard connectors at the user end. The CPU mating connector includes integral latches for enhanced reliability. Each ribbon cable has 40 wires.

  • Page 12: Table 2: J3 - Main I/O Connector

    Table 2: J3 – Main I/O Connector Notes on J3 Signals COM1 – COM4 The signals on these pins are RS-232 level signals and may be connected directly to RS-232 devices. The pin out of these signals is designed to allow a 9-pin male IDC connector to be crimped onto the corresponding ribbon cable wires to provide the correct pin out for a PC serial port connector (DTE).
  • Page 13 Board-mount socket: 3M / Robinson Nugent no. P50-080S-R1-TG, DSC no. 580884 Elektra CPU User Manual V1.00 Page 13...

  • Page 14: Input Power - J11

    A short press on the switch will turn on power, and holding the switch on for 4 seconds or longer will turn off power. Diamond Systems’ cable no. 6981009 mates with J11. It provides 9 color-coded wires with stripped and tinned leads for connection to user-supplied power sources. This cable may also be used with Diamond Systems’...

  • Page 15: Output Power - J12

    Common Common Table 5: J4 – Ethernet Connector Pin out J4 is a 1x6 pin header. It mates with Diamond Systems’ cable no. 6981002, which provides a panel-mount RJ-45 jack for connection to standard CAT5 network cables. Connector Part Numbers J11 Connector on CPU board: Digi-Key Corp.
  • Page 16 J5 Connector on CPU board: Standard 2x5, 0.1” header (with pin 1 removed) J5 Mating Cable Connector: Oupiin 4072-2X5H (Standard PC USB Header Interface) Elektra CPU User Manual V1.00 Page 16...

  • Page 17: Watchdog Features - J6

    Table 8: J8 – IDE Drive Connector Pin out J8 is a 2x22 (44-pin) 2mm-pitch pin header. It mates with Diamond Systems’ cable no. 6981004, and may be used to connect up to 2 IDE drives (hard disks, CD-ROMs, or flashdisk modules).

  • Page 18: Data Acquisition I/O Connector - J14 (Models With Data Acquisition Only)

    4.8 Data Acquisition I/O Connector – J14 (Models with Data Acquisition only) ELEKTRA includes a 50-pin header labeled J14 for all data acquisition I/O. This header is located on the left side of the board. Pin 1 is the lower right pin and is marked on the board. Diamond Systems’...

  • Page 19: Auxiliary Serial Port Connector - J15

    4.9 Auxiliary Serial Port Connector – J15 RX COM1 Pin 2 on DB9 #1 TX COM1 Pin 3 on DB9 #1 Ground Pin 5 on DB9 #1 RX COM2 Pin 2 on DB9 #2 TX COM2 Pin 3 on DB9 #2 Ground Pin 5 on DB9 #2 Table 10: J15 –...

  • Page 20: Jumper Settings

    5. JUMPER SETTINGS Refer to the ELEKTRA board drawing on page 9 for locations of the configuration items mentioned here. See page 22 for information on configuration J13 for the data acquisition circuit. 5.1 System Configuration J10 Jumper block J10 is used for configuration of IRQ levels, wait states, ATX power control, and CMOS RAM.
  • Page 21 The different configurations for J10 are shown below. Each illustration shows only the jumper of interest. An asterisk (*) indicates the default setting. Elektra CPU User Manual V1.00 Page 21...

  • Page 22: J13: Data Acquisition Circuit Configuration

    5.2 J13: Data Acquisition Circuit Configuration Jumper block J13 is used to configure the A/D and D/A circuits of the ELEKTRA. It is located on the left side of the board next to the data acquisition I/O pin header and is oriented horizontally. The functions are shown below and are described in detail on the following page.

  • Page 23: J6: Watchdog Timer & System Recovery

    Single-ended / Differential Inputs ELEKTRA can accept both single-ended and differential inputs. A single-ended input uses 2 wires, input and ground. The measured input voltage is the difference between these two wires. A differential input uses 3 wires: input +, input -, and ground. The measured input voltage is the difference between the + and - inputs.

  • Page 24: System Features

    6. SYSTEM FEATURES 6.1 System Resources The table below lists the default system resources utilized by the circuits on ELEKTRA. Device Address (Hex) ISA IRQ ISA DMA Serial Port COM1 I/O 3F8 – 3FF Serial Port COM2 I/O 2F8 – 2FF Serial Port COM3 I/O 3E8 –...

  • Page 25: Com Port / Fpga / Watchdog Control Registers

    6.2 COM Port / FPGA / Watchdog Control Registers A registers located at address 0x25F is used for the purposes of controlling the serial port, FPGA and watchdog features: Register Map Bit Assignments A blank bit in the write registers is unused. A blank bit in the read registers reads back as 0 or 1, unknown state.

  • Page 26: Console Redirection To A Serial Port

    6.3 Console Redirection to a Serial Port In many applications without a video card it may be necessary to obtain keyboard and monitor access to the CPU for configuration, file transfer, or other operations. ELEKTRA supports this operation by enabling keyboard input and character output onto a serial port (console redirection). A serial port on another PC can be connected to the serial port on ELEKTRA with a null modem cable, and a terminal emulation program (such as HyperTerminal) can be used to establish the connection.

  • Page 27: Flash Memory

    6.4 Flash Memory ELEKTRA contains a 2Mbyte 16-bit wide flash memory chip for storage of BIOS and other system configuration data. 256 KB of this space is used by BIOS software and the rest is free. However, the standard Elektra BIOS v1.00 does not integrate this feature and would require a custom BIOS to use this space for virtual disk drive simulation or other applications.

  • Page 28: Bios

    7. BIOS 7.1 BIOS Settings ELEKTRA uses a BIOS from Phoenix Technologies modified to support the custom features of the ELEKTRA board. Some of these features are described here. To enter the BIOS during system startup (POST – power on self-test), press F2. Serial Ports -The address and interrupt settings for serial ports COM1, COM2, COM3, and COM4 may be modified.
  • Page 29 - On the PCI and ISA Configuration pages (from the Advanced screen), the following setting should be retained: PCI IRQ Level 1-4 Autoselect for all PCI/PNP ISA UMB Region Exclusion Available for all -The Power Management Screen will only be in effect when under DOS. Otherwise, the OS power management settings will pre-empt these settings.

  • Page 30: Bios Console Redirection Settings

    7.2 BIOS Console Redirection Settings For applications where the Video interfaces will not be used, the textual feedback typically sent to the monitor can be redirected to a COM PORT. In this manner, a system can be managed and booted without the need for any video connection.

  • Page 31: System I/O

    6-pin header (J4) on the right edge of the board. Diamond Systems’ cable no. 6981002 mates with the header and provides a standard RJ-45 connector in panel-mount form for connecting to standard Cat5 network cables.

  • Page 32: Ps/2 Ports

    The settings of COM1 and COM2 may be changed in the system BIOS. Select the Advanced menu, then I/O Device Configuration. The base address and interrupt level may be modified on this page. The addresses of COM3 and COM4 are fixed. The interrupt (IRQ) settings for COM3 and COM4 are selected with J10.

  • Page 33: Notes On Operating Systems And Booting Procedures

    9. NOTES ON OPERATING SYSTEMS AND BOOTING PROCEDURES 9.1 Windows Operating Systems Installation Issues Installation of Windows operating systems ( Win98 ) should follow the sequence below. If the sequence is not followed certain drivers might not work and may prevent the device from functioning properly under Windows.

  • Page 34: Dos Operating Systems Installation Issues

    9.2 DOS Operating Systems Installation Issues Installation of DOS operating systems ( MS-DOS, FreeDOS, ROM-DOS ) should follow the sequence below. 1) Enable the following in BIOS: Legacy USB support. 2) Change BIOS boot sequence so system boots through USB floppy drive. 3) Insert DOS installation floppy disk into USB floppy drive and start/restart system.

  • Page 35: Data Acquisition Circuit - I/O Map And Register Descriptions

    10. DATA ACQUISITION CIRCUIT – I/O MAP AND REGISTER DESCRIPTIONS Elektra contain a data acquisition subsystem consisting of A/D, D/A, digital I/O, and counter/timer features. This subsystem is equivalent to a complete add-on data acquisition module. The A/D section includes a 16-bit A/D converter, 16 input channels, and a 128-sample FIFO. Input ranges are programmable, and the maximum sampling rate is 100KHz.
  • Page 36 The data acquisition circuitry on ELEKTRA occupies a block of 16 bytes in I/O memory space. The default address range for this block is 280h – 28Fh (base address 280). The data acquisition FPGA can be enabled/disabled in the BIOS under the Advanced menu, I/O devices.

  • Page 37: Data Acquisition Circuit Register Map

    10.2 Data Acquisition Circuit Register Map WRITE (Blank bits are unused and have no effect) Address STRTAD RSTBRD RSTDA RSTFIFO CLRDMA CLRT CLRD CLRA Enhanced Features Access Register SCANEN CKSEL1 CKFRQ1 CKFRQ0 ADCLK DMAEN TINTE DINTE AINTE DACH1 DACH0 DA11 DA10 DIOCTR DIRA...
  • Page 38 Page 1, WRITE (Blank bits are unused and have no effect) Address EE_EN EE_RW RUNCAL CMUXEN TDACEN EEPROM Access Key Register Page 1, READ (Blank bits are unused and read back as 0) Address TDBUSY EEBUSY CMUXEN TDACEN FPGA Revision Code Page 2, WRITE (Blank bits are unused and have no effect) Address...

  • Page 39: Register Bit Definitions

    10.3 Register Bit Definitions In these register definitions, a bit left blank is an unused bit. All unused bits in readable registers read back as 0. Base + 0 Write Command Register Bit No. Name STRTAD RSTBRD RSTDA RSTFIFO CLRDMA CLRT CLRD CLRA...
  • Page 40 Base + 0 Read A/D LSB Bit No. Name AD7 - 0 A/D data bits 7 - 0; AD0 is the LSB; A/D data is an unsigned 16-bit value. The A/D value is derived by reading two bytes from Base + 0 and Base + 1 and applying the following formula: A/D value = (Base + 0 value) + (Base + 1 value) * 256 The value is interpreted as a twos complement 16-bit number ranging from –32768 to +32767.
  • Page 41 Base + 2 Read/Write A/D Channel Register Bit No. Name H3 – H0 High channel of channel scan range Ranges from 0 to 15 in single-ended mode, 0 - 7 in differential mode. L3 - L0 Low channel of channel scan range Ranges from 0 to 15 in single-ended mode, 0 - 7 in differential mode.
  • Page 42 Base + 3 Write Analog Input Gain Bit No. Name SCANEN SCANEN Scan mode enable: Each A/D trigger will cause the board to generate an A/D conversion on each channel in the range LOW – HIGH (the range is set with the channel register in Base + 2).
  • Page 43 Base + 3 Read Analog Input Status Bit No. Name WAIT DACBSY SCANEN A/D status. 1 = A/D conversion or scan in progress, 0 = A/D is idle. If SCANEN = 0 (single conversion mode), STS goes high when an A/D conversion is started and stays high until the conversion is finished.
  • Page 44 Base + 4 Read/Write Interrupt / DMA / Counter Control Bit No. Name CKSEL1 CKFRQ1 CKFRQ0 ADCLK DMAEN TINTE DINTE AINTE CKSEL1 Clock source selection for counter/timer 1: 0 = internal oscillator, frequency selected by CLKFRQ1 1 = external clock input CLK1 (DIO C pins must be set for ctr/timer signals) CKFRQ1 Input frequency selection for counter/timer 1 when CKSEL1 = 1: 0 = 10MHz, 1 = 100KHz...
  • Page 45 Base + 6 Write DAC LSB Bit No. Name DA7–0 D/A data bits 7 - 0; DA0 is the LSB. D/A data is an unsigned 12-bit value. This register must be written to before Base + 7, since writing to Base + 7 updates the DAC immediately.
  • Page 46 OVF Overflow flag: Chapter 2 FIFO has overflowed; data has been lost. This flag is cleared on the next successful A/D read. FIFO has not overflowed since the last time A/D data was read Elektra CPU User Manual V1.00 Page 46...
  • Page 47 Base + 7 Write DAC MSB + Channel No. Bit No. Name DACH1 DACH0 DA11 DA10 DACH1–0 D/A channel. The value written to Base + 6 and Base + 7 are written to the selected channel, and that channel is updated immediately. The update takes approximately 20 microseconds due to the DAC serial interface.
  • Page 48 Base + 8 Read / Write Digital I/O Port A Bit No. Name Base + 9 Read / Write Digital I/O Port B Bit No. Name Base + 10 Read / Write Digital I/O Port C Bit No. Name These 3 registers are used for digital I/O. The direction of each register is controlled by bits in the register below.

  • Page 49: Counter/Timer Access

    10.3.1 PAGE 0: COUNTER/TIMER ACCESS Page 0, Base + 12 Read/Write Counter/Timer D7 - 0 Bit No. Name This register is used for both Counter 0 and Counter 1. It is the LSB for both counters. When writing to this register, an internal load register is loaded. Upon issuing a Load command through Base + 15, the selected counter’s LSB register will be loaded with this value.
  • Page 50 Page 0, Base + 15 Write Counter/Timer Control Register Bit No. Name CTRNO LATCH GTDIS GTEN CTDIS CTEN LOAD This register is used to control the counter/timers. A counter is selected with bit 7, and then a 1 is written to any ONE of bits 6 – 0 to select the desired operation for that counter. The other bits and associated functions are not affected.
  • Page 51 Page 0, Base + 15 Read FPGA Revision Code Bit No. Name REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 This register is used to control the counter/timers. A counter is selected with bit 7, and then a 1 is written to any ONE of bits 6 –...

  • Page 52: Auto Calibration Registers

    10.3.2 PAGE 1: AUTO CALIBRATION REGISTERS Page 1, Base + 12 Read/Write EEPROM / TrimDAC Data Register Bit No. Name D7-0 Calibration data to be read or written to the EEPROM and/or TrimDAC. During EEPROM or TrimDAC write operations, the data written to this register will be written to the selected device.
  • Page 53 Page 1, Base + 14 Write Calibration Control Register Bit No. Name EE_EN EE_RW RUNCAL CMUXEN TDACEN This register is used to initiate various commands related to auto calibration. More detailed information on auto calibration may be found elsewhere in this manual. EE_EN EEPROM Enable.
  • Page 54 Page 1, Base + 15 Write EEPROM Access Key Register The user must write the value 0xA5 (binary 10100101) to this register each time after setting the PAGE bit in order to get access to the EEPROM. This helps prevent accidental corruption of the EEPROM contents.

  • Page 55: Expanded Fifo And Jumper Over Ride

    10.3.3 PAGE 2: EXPANDED FIFO AND JUMPER OVER RIDE Page 2, Base+12 Read/Write Expanded FIFO Control Bit No. Name EXPFIFO EXPFIFO Expanded FIFO control This is the default value. EXPFIFO is also set to this value when enhanced features are disabled. In this mode, the FIFO interface acts identically to the Prometheus.
  • Page 56 Page 2, Base+13 Write/Read Jumper override Bit No. Name ADUOUT ADUOEN SDOUT SDOEN SDOEN SE/DIFF output enable: If this bit is enabled the register setting of SDOUT will override J13 jumper setting for SE/DIFF (single-ended/differential) SE/DIFF determined by SDOUT SE/DIFF determined by J13 jumper setting [default] SDOUT SE/DIFF value: Single-Ended...

  • Page 57: Analog-To-Digital Input Ranges And Resolution

    11. ANALOG-TO-DIGITAL INPUT RANGES AND RESOLUTION 11.1.1 OVERVIEW ELEKTRA uses a 16-bit A/D converter. The full range of numerical values for a 16-bit number is 0 - 65535. However the A/D converter uses twos complement notation, so the A/D value is interpreted as a signed integer ranging from –32768 to +32767.

  • Page 58: Performing An A/D Conversion

    12. PERFORMING AN A/D CONVERSION This chapter describes the steps involved in performing an A/D conversion on a selected input channel using direct programming (not with the driver software). There are seven steps involved in performing an A/D conversion: 1. Select the input channel 2.

  • Page 59: Perform An A/D Conversion On The Current Channel

    12.4 Perform an A/D conversion on the current channel After the above steps are completed, start the A/D conversion by writing to Base + 0. This write operation only triggers the A/D if AINTE = 0 (interrupts are disabled). When AINTE = 1, the A/D can only be triggered by the on-board counter/timer or an external signal.

  • Page 60: Convert The Numerical Data To A Meaningful Value

    12.7 Convert the numerical data to a meaningful value Once you have the A/D value, you need to convert it to a meaningful value. The first step is to convert it back to the actual measured voltage. Afterwards you may need to convert the voltage to some other engineering units (for example, the voltage may come from a temperature sensor, and then you would need to convert the voltage to the corresponding temperature according to the temperature sensor’s characteristics).

  • Page 61: A/D Scan, Interrupt, And Fifo Operation

    The table on the next page describes the board’s behavior for each of the 4 possible cases of AINTE and SCANEN. The given interrupt software behavior describes the operation of the Diamond Systems Universal Driver software. If you write your own software or interrupt routine you should conform to the described behavior for optimum results.

  • Page 62: Elektra A/D Operating Modes

    13.1 ELEKTRA A/D Operating Modes The following control bits and values are referenced in the descriptions in the table below. AINTE Base + 4 bit 0 SCANEN Base + 3 bit 2 FIFO threshold Base + 5 bits 5-0 Base + 3 bit 7 LOW, HIGH 4-bit channel nos.

  • Page 63: Analog Output Ranges And Resolution

    14. ANALOG OUTPUT RANGES AND RESOLUTION 14.1 Description ELEKTRA uses a 4-channel 12-bit D/A converter (DAC) to provide 4 analog outputs. A 12-bit DAC can generate output voltages with the precision of a 12-bit binary number. The maximum value of a 12-bit binary number is 2 - 1, or 4095, so the full range of numerical values that the DACs support is 0 - 4095.

  • Page 64: D/A Conversion Formulas And Tables

    14.4 D/A Conversion Formulas and Tables The formulas below explain how to convert between D/A codes and output voltages. D/A Conversion Formulas for Unipolar Output Ranges Output voltage = (D/A code / 4096) * Reference voltage D/A code = (Output voltage / Reference voltage) * 4096 Example: Output range in unipolar mode = 0 –...
  • Page 65 D/A Conversion Formulas for Bipolar Output Ranges Output voltage = ((D/A code – 2048) / 2048) * Output reference D/A code = (Output voltage / Output reference) * 2048 + 2048 Output range in bipolar mode = ±10V Example: Full-scale range = 10V – (-10V) = 20V Desired output voltage = 2.000V D/A code = 2V / 10V * 2048 + 2048 = 2457.6 =>...

  • Page 66: Generating An Analog Output

    15. GENERATING AN ANALOG OUTPUT This chapter describes the steps involved in generating an analog output (also called performing a D/A conversion) on a selected output channel using direct programming (not with the driver software). There are three steps involved in performing a D/A conversion: 1.

  • Page 67: Calibration

    16. ANALOG CIRCUIT CALIBRATION RESOURCES For a board with the Data Acquisition option, the Elektra Data Acquisition circuitry incorporates some advanced calibration features to allow the system to calibrate both the A/D and D/A signal conversion pathways. The registers involved in controlling these calibration features are listed below: Register Register location...

  • Page 68: A/D Bipolar Offset

    OUTPUT (TrimDAC Address) NAME FUNCTION POLARITY A/D offset, all modes, The same for bipolar, ADCOFF coarse coarse Inversed for unipolar The same for bipolar, ADCOFF fine A/D offset, fine Inversed for unipolar A/D full scale, all modes, ADCFUL coarse coarse Inversed ADCFUL fine A/D full scale, fine...

  • Page 69: Using Eeprom

    16.2 Using EEPROM There is an EEPROM used to store all TrimDAC adjustment values. These values are loaded on reset or power-up, so it is critical that these values be correct in order to maintain accurate A/D measurements. These settings are configured to defaults during manufacturing test – be sure that you know what you are doing before changing these settings.

  • Page 70: Digital I/O Operation

    17. DIGITAL I/O OPERATION ELEKTRA contains 24 digital I/O lines organized as three 8-bit I/O ports, A, B, and C. The direction for each port is programmable, and port C is further divided into two 4-bit halves, each with independent direction. The ports are accessed at registers Base + 8 through Base + 10 respectively, and the direction register is at Base + 11.

  • Page 71: Counter/Timer Operation

    18. COUNTER/TIMER OPERATION ELEKTRA contains two counter/timers that provide various timing functions on the board for A/D timing and user functions. These counters are controlled with registers in the on-board data acquisition controller FPGA. See pages 44 and 50 for information on the counter/timer control register bits and how to perform various functions using these counters.

  • Page 72: Command Sequences

    18.3 Command Sequences Diamond Systems provides driver software to control the counter/timers on ELEKTRA. The information here is intended as a guide for programmers writing their own code in place of the driver and also to give a better understanding of the counter/timer operation.
  • Page 73 Reading a counter a. Latch the counter: Counter 0 Counter 1 outp(base+15,0x40); outp(base+15,0xC0); b. Read the data: The value is returned in 3 bytes, low, middle, and high (2 bytes for counter 1) Counter 0 Counter 1 low=inp(base+12); low=inp(base+12); middle=inp(base+13); high=inp(base+13);...

  • Page 74: Watchdog Timer Programming

    19. WATCHDOG TIMER PROGRAMMING 19.1 Watchdog Timer ELEKTRA contains a watchdog timer circuit consisting of one programmable timer, WDT. The input to the circuit is WDI, and the output is WDO. Both signals appear on the watchdog connector J6. WDI may be triggered in hardware or in software. A special “early” version of WDO may be output on the WDO pin.

  • Page 75: Watchdog Timer Register Details

    19.2 Watchdog Timer Register Details 0x25C Write WDT Trigger Register Bit No. WDTRIG Name WDTRIG Writing a 1 to this bit triggers an immediate software reload of the WDT watchdog timer. 0x25C Read WDT Trigger Register This register does not read back. 0x25D Write WDT Counter Register...
  • Page 76 0x25E Write WDT Control Register Bit No. WDIEN WDOEN WDSMI WDEDGE Name WDIEN 0 = Disable edges on the WDI pin retriggering WDT. 1 = Enable egdes on the WDI pin retriggering WDT. WDOEN 0 = Disable edge on WDO pin when WDT reaches 1. 1 = Enable edge on WDO pin when WDT reaches 1.

  • Page 77: Example : Watchdog Timer With Software Trigger

    19.3 Example : Watchdog Timer With Software Trigger Software trigger relies on a thread of execution to constantly trigger WDT. If the thread is ever halted, WDT will reach zero and initiate the reset sequence. In this example we will set the watchdog timer to a countdown period of 2.175 seconds. Note that longer timeout periods should typically be used when relying on software-based triggers for the Watchdog Timer in order to accommodate varying software latencies (interrupt latencies, other tasks with priority at certain times, etc)

  • Page 78: Data Acquisition Specifications

    20. DATA ACQUISITION SPECIFICATIONS These specifications apply to units with Data Acquisition Only Analog Inputs No. of inputs 8 differential or 16 single-ended (user selectable) A/D resolution 16 bits (1/65,536 of full scale) ±10V, ±5V, ±2.5V, ±1.25V Input ranges Bipolar: Unipolar: 0-8.3V, 0-5V, 0-2.5V Input bias current...

  • Page 79: Flashdisk Module

    The power may be provided from the CPU’s power out connector (J12) or from one of the two 4-pin headers on the ACC-IDEEXT board. Diamond Systems’ cable no. 6981006 may be used with either power connector to bring power to the drive.

  • Page 80: Flash Disk Programmer Board

    This operation is normally done at system setup. The board can also be used to enable the simultaneous connection of two drives to the CPU. J1 connects to the IDE connector on ELEKTRA with a 44-pin ribbon cable (Diamond Systems’ part no. 6981004). Both 40-pin .1” spacing (J4) and 44-pin 2mm spacing (J3) headers are provided for the external hard drive or CD-ROM drive.

  • Page 81: I/O Cables

    23. I/O CABLES Diamond Systems offers a cable kit no. C-ELK-KIT with 10 cables to connect to all I/O headers on the board. Some cables are also available separately. The mating cable for each I/O connector is listed in Chapter 4.

  • Page 82: Quick Start Guide

    24. QUICK START GUIDE This section will describe the steps necessary to get your ELEKTRA up and running. It is assumed that you have also purchased the ELEKTRA Development Kit. This kit includes all cables described on on page 81, a power supply, USB floppy drive, mounting hardware, IDE flashdisk and the flashdisk programmer board.

  • Page 83: Booting Into Ms-Dos, Freedos Or Rom-Dos

    24.3 Booting into MS-DOS, FreeDOS or ROM-DOS This section describes how to boot into a DOS-based operating system via a bootable floppy disk. 1) Plug the USB floppy drive into one of the USB terminals of cable 6981012 (see step 7.) 2) Insert your DOS-based boot disk into the USB floppy drive.

This manual is also suitable for:

Elektra fd-32Elektra fd-128Elektra fd-96Elektra fd-256

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