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Schematic Diagrams
Power V-Core1
VCORE_1
Sheet 37 of 44
Power V-Core1
[ 5]
[11,15, 28]
[28]
VCORE_ON
B - 38 Power V-Core1
PR311
H _PROC HOT#
PR314
750_1%_04
[3]
H _PR OCH OT#
1.05VS
VR_RDY A
PR325
10K_04
10_1%_04
3.3VS
D ELAY _PWR GD
PR339
10K_04
PR313
[15]
DELAY _PWR GD
[6]
VCC_GT_SENSE
1.05VS
[6]
VSS_GT_SEN SE
PR328
PR329
PR 330
130_1%_04
75_1%_04
54.9_1%_04
H_C PU_SVI DDAT
[5]
H_CPU_SVIDDAT
H_C PU_SVI DALRT#
H _CPU_SVIDALR T#
H_C PU_SVI DCLK
5VS
[5]
H_CPU_SVIDC LK
APGND
PJ 14 *OPEN_1mm
1
2
PR 333
10K_04
APGND
PR 334
90.9K_1%_04
APGND
PR 337
1K_04
VIN
PC317
0.01u_50V_X7R_04
APGND
PR342
*10mil_04
[5]
VCORE_VSS_SENSE
PC 319
PR346
*10mil_04
1000p_50V_X7R _04
[5]
VCORE_VCC_SENSE
PR 349
PR 351
PC324
PR 350
10_1%_04
680p_50V_X7R _04
49.9_1%_04
100p_50V_NPO_04
TRBST#
PR353
1.21K_1%_04
PR354
PC329
4700p_50V_X7R _04
PR 7
*10mil_04
APGND
ALL_SY S_PWRGD
VR_EN
PR 355
*10K_04
3.3VS
1
2
PR357
6
PJ 9
* 100K_04
*OPEN _1mm
D
PQ101A
PR360
2
G
3
S
PQ101B
*10K_04
1
*MTDK5S6R
D
*MTDK5S6R
PJ4
5
G
* OPEN_1mm
S
4
PC333
* 0.1u_16V_Y 5V_04
PC 302
0.1u_10V_X7R_04
R T1
APGND
PR 308
24. 3k_1%_04
APGND
PC306
PC307
10p_50V_NPO_04
PR312
33p_50V_N PO_04
PR315
PC 308
165K_1%_04
1K_1%_04
4.3K_1%_04
2200p_50V_X7R _04
0710 D02
PR316
66.5K_1%_06
SW N1A [38]
5VS
APGN D
PR318
*10m il_04
PC310
PC 309
1000p_50V_X7R_04
PR371
*10m il_04
1000p_50V_X7R _04
CSREFA
CSREF A [ 38]
PC311
0.1u_10V_X7R_04
APGND
PR323
* 10m il_04
APGND
PR326
23.2K_1%_04
PR327
2_06
1
45
PC313
2. 2u_6.3V_X5R_04
VCC
PW MA
2
44
PR 331
VDD BP
BSTA
VR_RD Y A
3
PU1
43
2_06
VRD Y A
H GA
VR_EN
4
42
NCP6132AMNR26
EN
SW A
H_CPU _SVI DDAT
5
41
6
SDIO
LGA
40
H_CPU _SVI DALRT#
PR 332
ALERT#
BST2
H_CPU _SVI DCLK
7
39
8
SCLK
HG2
38
VBOOT
VBOOT
SW 2
9
37
ROSC
LG2
10
36
11
VRMP
PVC C
35
H_PROCHOT#
VRH OT#
PGN D
DELAY _PWRGD
12
34
LG1 [38]
13
VRD Y
LG1
33
VSN
VSN
SW 1
VSP
14
32
HG1 [38]
VSP
HG1
15
31
PR 338
DIFF
BST1
2_06
PR343 27.4K_1%_04
PC320
0.1u_10V_X7R_04
APGN D
PC322
33p_50V_NPO_04
CSP1
1K_1%_04
CSP2
PC325
PR 352
CSP3
4.12K_1%_04
PC326
10.7K_1%_04
4700p_50V_X7R_04
CSREF
CSREF [38]
PC327
1000p_50V_X7R_04
C SSU M
APGND
PR358
PC330
0710 D02
PC331
1000p_50V_X7R _04
PR359
PC332
680p_50V_X7R_04
PR361
PR362
PR363
APGND
APGN D
75K_1%_04
165K_1%_04
RT4
2
1
PUT COLSE
TO VCORE
100K_NTC_06_A
Phase 1
[3,9,10,11, 12,13,14,15, 16,17,18,19,20,23,24, 25,28,29,30, 31,32]
Inductor
PUT COLSE
PR310
PC305
TO GT
1.65K_1%_06
1000p_50V_X7R_04
CSC OMPA
DROOPA
Inductor
TSENSEA
RT2
PR321
CSREF A
PC312
0. 047u_10V_X7R_04
CSP1A
PR324
6.98K_1%_04
SW N1A [38]
PUT COLSE
TO VGFX
HOT SPOT
PC 314
0.22u_10V_X5R _04
5VS
HG1A [38]
SW1A [38]
LG1A [38]
PC 315
0.22u_10V_X5R_04
2_06
HG2 [38]
SW2 [38]
PR335
PR336
Option for
LG2 [38]
PC 316
2.2u_6.3V_X5R_04
1 phase
*0_04
0_04
5VS
CSP1A
SW1 [38]
CSP2A
PC 318
0.22u_10V_X5R_04
5VS
Option for
PR 341
2 phase
CPU
*10mil_04
CSP1
PR345
6.98K_1%_04
SWN 1 [38]
CSP3
PC 321
0.047u_10V_X7R_04
CSREF
CSP2
PR20
6.98K_1%_04
SWN 2 [38]
PC 323
0.047u_10V_X7R_04
CSREF
PR356
PC 328
2.43K_1%_04
1000p_50V_X7R_04
CSCOMP
DR OOP
CSREF
165K_1%_06
SWN 1 [38]
165K_1%_06
SWN 2 [38]
[ 13,14,15,19, 20,35]
1.05VS
[11,32, 33,34,35,36, 38,39]
VIN
[12, 13,20,25,30, 31,32]
5VS
3.3VS
CSREFA
GT
TSENSE
PR344
RT3
PUT COLSE
TO VCORE
HOT SPOT
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