HDSL MAINTENANCE MODES
This Appendix describes operation of the HDSL
system with regard to detection of in-band and ESF
facility data link loopback codes.
Upon deactivation of a loopback, the HDSL system
will synchronize automatically. Note that the
synchronization process of the HDSL system upon
deactivation of the HRE loopback could take up to
15 seconds, ensuring all system elements are
synchronized.
Loopback Process Description
In general, the loopback process for the HDSL
system elements is modeled on the corresponding
DS1 system process. Specifically, the HTU-C
loopback is similar to an Intelligent Office Repeater
loopback, and the HTU-R loopbacks are similar to
an inline T1 Repeater loopback.
In-band control code sequences are transmitted over
the DS1 link by either the insert or overwrite
method. The HDSL elements respond to either
method. The insert method produces periodic
control sequences that are not overwritten by the
DS1 framing bits. The overwrite method produces
periodic control sequences. However, once per
frame, the framing bit overwrites one of the bits in
the control sequence. The unit can detect the
loopback activation or deactivation code sequence
only if an error rate of 1E
61245001L6-5G
Appendix A
HDSL Loopbacks
-03
or better is present.
Section 61245001L6-5, Issue 7
DDS Latching Loopback Operation
If the unit is optioned for FT1 mode, then DDS
Latching Loopback operation is supported as
described in Bellcore TA-TSY-000077, Issue 3,
Section 5.1.3. The HTU-C and any HRE units
which are in the HDSL circuit are treated as
Identical Tandem Dataports, and the HTU-R is
treated as a Different Tandem Dataport. For a
complete description of the DDS Latching
Loopback codes, refer to Bellcore TA-TSY-000077,
Issue 3, Section 5.1.3.
Loopback Control Codes
Control sequences are summarized in Table A-1
and Table A-2.
NOTE
In all control code sequences presented, the
in-band codes are shown with the left-most bit
transmitted first, and the ESF data link codes
with right-most bit transmitted first.
A-1
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