HP 5501A Operating And Service Manual page 99

Table 3-3. Typical comparator-Based Computer lnterface System Specifications (Continued)
I
Error Check:
External: TTL level signals are available when Reference or Measurement errors
are detected.
ystem Controller: An error code is
10746
Binary tnterface for Reference o
10762A COMPARATOR
Input Signal: Up/down or Phase-quadrature (A-Quad-6) Pulses. Minimum 50 nano-
second pulse width, maximum 10 MHz.
Measurement Accuracy: kO.5 PPM + I count in conjunction with 5501A Laser Trans-
ducer and 107648 Fast Pulse Converter.
rt2
counts if hysteresis circuit selected.
Destination and Toler
7..
,,-
Input Rate: Nine individual operations at typically
I
microsecond each are re-
quired to transfer two 32-bit words from the system controller to two 10762A
Comparators using the two 16-bit word format in conjunction with the 10746A
Binary Interface.
Digital Difference Output: Available at card edge connector.
Null Outpuk Occurs when the 28-bit counter agrees with the 28-bit destination with-
4
in the four tolerance bits (215 counts). This signal is available both externally at the
-
card edge connector and to the system controller via the 10746A Binary Interface.
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External Null Output: TTL level change, active low.
Response: 1.1 micr microseconds typical
System Null: Availab
a null condition.
Zero Speed Output: Occurs when no counts have entered the Up/Down Counter
within 17 msec (variable from
1
to 100 msec); TTL level change, active high.
Reset: Initializes Up/Down counter at 160 counts. Can
be
initiated either externally
or by the system controller via the 107468 Binary Interface. Reset also activates a Forced
Null condition on the Digital Difference Output.
External: TTL level change, active low. Reset condi
returned to the high state.
ystem Controller: The co
all 1076% Comparator
under program control.
Sample: Places Upmown counter contents in output buffer for transfer to system
controller. Also releases the forced Null on the digital difference output after load-
ing destination and tolerance. Can be initiated either externally or by the system
controller via the 10746A Binary Interface.
Externak l l L level change; active low. Minimum 40 nanosecond pulse width.