Table of Contents
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Table
4-7.
70762A
Comparator
lnstructions
BACKPLANE
ADDRESS
IS
SELECTABLE,
MAY
BE
X,
Y,
Z,
A,
B,
OR
C
(Mutually
~xclusive)
-
ADDRESSED
INSTRUCTIONS
I
Instruction
I
Response
D i a l
1
I
Instruction
*Ox
I
Preset
count
register
to
160
counts,
force
digital
difference
output
to
null,
clear
OVFL-BUFFER,
terminate
self-check
(if
in
progress)
Load
contents
of
counter
into
output buffer
a s
soon
a s
there
is
a
window
wide
enough
to
insure
that
a
count
is
not
propagating
through
the
count
chain
W
Output
contents
of
output
buffer
to
backplane
data
bus,
output
A
mode
(A/4
or
Ah),
output
decimal
point
code,
output
contents
of
OVFL-ERROR
buffer.
Data
valid
signal
goes
true
only
if
sample
circuit
is
not
in
the
process
of
taking
a
sample
Load
destination register
with
28-bit
number
and
tolerance
*ter
with
4bit
number
on 10740A
backplane
when
binary
DAV
goes
true.
X
is
i m ~ l i e d
Listener
-
10746A
i m ~ l i e d
Talker
Disable
UP/A
and
DWN/B
inputs
and
count
down
at
10
MHz.
(Terminates
with
a
reset,
or
an
underflow
in
count
register)
1 '
5X
I
NOP
6X
NOP
7X
Disable
UP/A
and
DWN/B
inputs
and
count
up at
10
MHz.
(Terminates
with
reset
or
an
overflow
in
count reisterl
Refer
to
Table
4-77
a s
instruction
is
address-
dependent
- -
NONADDRESSED
INSTRUCIIONS
1
1
System
Reset
I
Same
a s BX
instruction
I
-
I
'
I
Sam~le
I
Same
a s
1X
instruction
I
-
I
--
*"X"
used
a s
an
example
of
the
address
in
this
table.
To
make
instruction
apply
to
another
comparator
simply
replace
"X"
with
that
card's
address.
Table
4-8.
707648
Fast
Pulse
Converter
Instructions
*"X"
used
a s
an
example
of
the
address
in
this
table.
To
make
instructions
apply
to
another fast
pulse
converter
simply
replace
"X"
with
that
card's
address.
At
least
two
reset
pulses
are
required
after
power
on
or
resolution
change.
BACKPLANE
ADDRESS
IS
SELECTABLE,
MAY
B E
X,
Y,
Z,
A,
B,
OR
C
(Mutuallv
exclusive^
ADDRESSED
INSTRUCTIONS
HP-IB
l
nstruction
*OX
2X
NONADDRESSED
INSTRUCTIONS
System
Reset
I
Same
a s
0X
instruction
I
-
Response
Reset
error
bits
and
samples
resolution
switches
Output
contents
of
buffer
register
error
bits
to
backplane
data
bus
Decimal
1
nstruction
Refer
to
Table
4-77
a s
instruction
is
address-
dependent
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