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Huawei FusionServer Pro CH225 V5 Compute Node
Technical White Paper
PCIe
Slot
PCIe
SSD
11
PCIe
SSD
12
PCIe
SSD
13
PCIe
SSD
14
Issue 06 (2020-07-31)
Displ
CPU
PCIe
ay on
Stan
BMC
dards
disk1
CPU
PCIe
1
2
3.0
disk1
CPU
PCIe
2
2
3.0
disk1
CPU
PCIe
3
2
3.0
disk1
CPU
PCIe
4
2
3.0
Copyright © Huawei Technologies Co., Ltd.
Conn
Bus
Port
ector
Widt
No.
Widt
h
h
x4
x4
Port
1C
(passi
ng
throu
gh
the
PCIe
Switc
h)
x4
x4
Port1
C
(passi
ng
throu
gh
PCIe
Switc
h)
x4
x4
Port1
A
(passi
ng
throu
gh
PCIe
Switc
h)
x4
x4
Port1
A
(passi
ng
throu
gh
PCIe
Switc
h)
5 Hardware Description
Root
Devic
Slot
Port
e
Size
(B/D/
(B/D/
F)
F)
85:02.
91:00.
2.5"
0
0
drive
85:02.
90:00.
2.5"
0
0
drive
85:00.
89:00.
2.5"
0
0
drive
85:00.
8a:
2.5"
0
00.0
drive
29
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