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Huawei FusionServer Pro CH225 V5 Compute Node
Technical White Paper
PCIe
Slot
Mezz
1
Mezz
2
Mezz
3
Mezz
4
PCIe
SSD 4
PCIe
SSD 5
Issue 06 (2020-07-31)
Displ
CPU
PCIe
ay on
Stan
BMC
dards
\
CPU
PCIe
1
3.0
\
CPU
PCIe
1
3.0
\
CPU
PCIe
2
3.0
\
CPU
PCIe
2
3.0
disk4
CPU
PCIe
1
3.0
disk5
CPU
PCIe
1
3.0
Copyright © Huawei Technologies Co., Ltd.
Conn
Bus
Port
ector
Widt
No.
Widt
h
h
x16
x16
Port2
or
or
A or
two
two
(Port
x8
x8
2A
+Port
2C)
x16
x16
Port3
or
or
A or
two
two
(Port
x8
x8
3A
+Port
3C)
x16
x16
Port2
or
or
A or
two
two
(Port
x8
x8
2A
+Port
2C)
x16
x16
Port3
or
or
A or
two
two
(Port
x8
x8
3A
+Port
3C)
x4
x4
Port
1C
(passi
ng
throu
gh
the
PCIe
Switc
h)
x4
x4
Port1
C
(passi
ng
throu
gh
PCIe
Switc
h)
5 Hardware Description
Root
Devic
Slot
Port
e
Size
(B/D/
(B/D/
F)
F)
3a:
3b:
-
00.0
00.0
3a:
3c:
02.0
00.0
5d:
5e:
-
00.0
00.0
5d:
5f:
02.0
00.0
ae:
af:
-
00.0
00.0
ae:
b0:00.
02.0
0
d7:00.
d8:00.
-
0
0
d7:02.
d9:00.
0
0
17:02.
1e:
2.5"
0
00.0
drive
17:02.
1f:
2.5"
0
00.0
drive
27
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