Uart Interfaces - Quectel LPWA Series Hardware Design

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4.4. UART Interfaces

Pin definition of the UART interface is shown as follows:
Table 16: Pin Definition of Main UART Interface
Pin Name
Pin No.
MAIN_DTR
30
MAIN_RXD
34
MAIN_TXD
35
MAIN_CTS
36
MAIN_RTS
37
MAIN_DCD
38
MAIN_RI
39
The module provides three UART interfaces and the following shows their features:
Table 17: UART Information
Parameters
Supported Baud
Rate
Default Baud Rate
Default frame format
Functions
BG950A-GL&BG951A-GL_Hardware_Design
I/O
Description
DI
Main UART data terminal ready
DI
Main UART receive
DO
Main UART transmit
DO
Main UART clear to send
DI
Main UART request to send
DO
Main UART data carrier detect
DO
Main UART ring indication
Main UART Interface
9600 bps, 19200 bps,
38400 bps, 57600 bps,
115200 bps, 230400 bps,
460800 bps, 921600 bps
and 3000000 bps
115200 bps
8N1 (8 data bits, no parity,
1 stop bit)
Data transmission
AT command
communication
RTS and CTS
hardware flow control
Debug UART Interface
9600 bps, 19200 bps,
38400 bps, 57600 bps,
115200 bps, 230400 bps,
460800 bps, 921600 bps
and 3000000 bps
115200 bps
8N1 (8 data bits, no parity,
1 stop bit).
Firmware upgrade
Software debugging
Log output
LPWA Module Series
Comment
1.8 V power domain
If unused, keep this pin open.
Auxiliary UART
Interface
-
921600 bps
8N1 (8 data bits, no
parity, 1 stop bit).
RF calibration
Log output
44 /89

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