Tandon TM100-1 Operating And Service Manual page 37

4.5 READ/WRITE DATA
The components of the drive required to read
and write data are:
1 . Read/Write Head Assembly
2 . Side Select circuits
3 . Write/Erase circuits
4. Read Data circuits
READ/WRITE HEAD ASSEMBLY
The read/write head(s) are glass bonded, ferrite
cores mounted in a ceramic structure. The lower
head structure is mounted in a fixed position to
a plastic carriage. The upper head is mounted to
a gimballed flexure to conform to the diskette.
The head carriage assembly is attached to the
chassis on guide rails. It is positioned by a split
band attached to the stepper motor.
SIDE SELECT CIRCUITS
The Side Select signal is derived from the host
controller via the interface connector Jl, Pin 32.
This signal is buffered. If the signal is high at
the interface, Side 0 is selected by applying a
voltage potential on the center tap of Head 0 ,
and allows current to flow in the coils of Head 0 .
If the signal at the interface is low, Side 1 , is
selected, by applying a voltage potential on the
center tap of Head 1 , allowing current to flow in
the coils of Head 1 .
In the read mode, a potential of + 5 volts D. C. is
applied to the selected head diode matrix. The
write mode increases the voltage applied to the
selected head diode matrix to +12 volts D. C.
from the beginning of Write Enable until the
end of Internal Write Busy.
WRITE/ERASE CIRCU ITS
The write electronics consist of a write current
source, a write waveform generator, an erase
current source, the trim erase control logic, and
the side select logic (Figure 4-7).
The signals required to control the data electron­
ics provided by the host controller are:
1 . Drive Select
2 . Write Enable
3 . Write Data
4 . Side Select
The winding on the head is center tapped.
During a write operation, current from the write
current source flows in alternate halves of the
winding, under control of the write waveform
generator.
When the drive is selected and write protect is
false, N Write Enable initiates the write logic.
Seven events that occur are (Figures 4-7 and
4-8):
1 . The pre-erase delay one shot is started,
390 microseconds.
2 . The post-erase delay one shot is started,
900 microseconds.
3 . The post-erase delay one shot outputs a
signal: N Internal Write Busy. It is used
to disable the Read Data output circuit,
and to increase the read/write diode
matrix voltage from 5 volts D. C. to 12
volts D. C. via the side select logic during
a write operation.
4 . The write current source is enabled only
when the +5 volts D. C. supplied to the
drive is at the correct value.
5 . The write waveform generator has its
preset and clear inputs set to +5 volts
D. C. instead of ground.
4-7