Tandon TM100-1 Operating And Service Manual page 21

Read/Write command is completed. When the
signal line logic level is false (high), the input
control lines and output status lines are disabled.
The drive address is determined by a jumper
select on the logic circuit board. Drive Select
lines 0 through 3 provide a means of daisy chain­
ing a maximum of four drives to a controller.
Only one can be true (low) at a time. An unde­
fined operation results if two or more drives are
assigned the same address or if two or more
Drive Select lines are in the true (low) state
simultaneously.
MOTOR ON
When this signal is true (low), the drive motor
accelerates to its nominal speed of 300 RPM,
and stabilizes at this speed in less than 250
milliseconds. When the signal line logic level
goes false (high), the drive decelerates to a stop.
This signal is not gated with Drive Select.
The motor activates momentarily when the
front latch is closed. This motor start function
remains active for approximately five seconds,
unless Motor On is in the true (low) condition.
DIRECTION SELECT AND STEP LINES
(TWO LINES)
When the drive is selected, a true (low) pulse on
the Step line, with a time duration greater than
200 nanoseconds, initiates the access motion.
The direction of motion is determined by the
logic state of the Direction Select line when a
step pulse is issued. The motion is toward the
center of the disk if the Direction Select line is
in the true Qow) state. The direction of motion is
away from the center of the disk if the Direction
Select line is in the false (high) state.
To ensure proper positioning, the Direction
Select line should be stable at least 100 nanosec­
onds prior to issuing a corresponding step pulse,
and remain true Qow) 100 nanoseconds after it.
The access motion is initiated on the trailing
edge of the step pulse. The time period between
consecutive trailing edges of step pulses should
be not less than five milliseconds.
The drive electronics ignore step pulses when
one of three conditions exists:
1 . The write enable is true Qow).
2 . The direction select is false (high), and
the head is positioned at Track 0 .
3 . The drive is not selected.
COMPOSITE WRITE DATA
When the drive is selected, this interface line
provides the bit serial composite write data
pulses that control the switching of the write
current in the selected head. The write elec­
tronics must be conditioned for writing by the
Write Enable line.
For each high-to-low transition on the Composite
Write Data line, a flux change is produced at the
write head gap. This causes a flux change to be
recorded on the media.
When a single-density (FM) type encoding tech­
nique is used in which data and clock form the
combined Write Data signal, it is recommended
that the repetition of the high-to-low transi­
tions, while writing all zeros, be equal to one-half
the maximum data rate, 125 kilohertz ±0.1
percent, and the repetition of the high-to-low
transitions, when writing all ones, be equal to
the maximum data rate, 250 kilohertz ±0.1
percent.
Host controllers may implement write precom­
pensation circuits that recognize worst case pat­
terns and adjust the write data waveform.
Although a value cannot be specified for write
precompensation, Tandon suggests a value of
250 nanoseconds for systems using MFM double
density recording format.
WRITE ENABLE
When this signal is true Qow), the write
electronics are prepared for writing data and
the read electronics are disabled. This signal
turns on write current in the selected read/write
head. Data is written under the control of the
Composite Write Data and Side Select input
lines. When the Write Enable line is false
(high), all write electronics are disabled.
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