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CAS # Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: Auto,3, 4 and 5.
RAS-to-CAS Delay
This field let's you insert a timing delay between the CAS and RAS strobe signals, used when DRAM
is written to, read from, or refreshed. Fast gives faster performance; and Slow gives more stable
performance. This field applies only when synchronous DRAM is installed in the system. The
settings are: 4T and 3T.
RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T.
3-7
Integrated Peripherals
> OnChip IDE Function
> OnChip Device Function
> OnChop Super IO Function
Init Display First
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
OnChip IDE Function
Please refer to section 3-7-1
OnChip Device Function
Please refer to section 3-7-2
OnChip Super IO Function
Please refer to section 3-7-3
Init Display First
This item allows you to decide to activate whether PCI Slot or AGP VGA first. The settings
are: PCI Slot, AGP Slot.
Phoenix – AwardBIOS CMOS Setup Utility
Integrated Peripherals
Press Enter
Press Enter
Press Enter
PCI Slot
F6:Optimized Defaults
Menu Level >
F7:Standard Defaults
37
Item Help
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