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and of port group #G, which can be able to access by 4 bit. /
(f) PCM Highway Controller Function / This function generates the
basic timing of PCM Highway, and eight channel pulses.
Following are the clocks generated. / CHS0 ~ 4: 128, 64, 32, 16, 8
kHz Channel select signal / CP0 ~ 5: 8 kHz Synchronous signal for
CODEC /
(g) APT Data Communication Circuit / APT Data Communication
Circuit is a circuit which performs the serial/parallel conversion of
the control data between APT comm. Paths and the main
CPU(IC100). This circuit covers 4 lines corresponding to each
extension, and 4 lines are integrated into on Gate Array(IC101). / /
/ / / / /
(h) DPT Data Communication Circuit / DPT Data Communication
Circuit is a circuit which has the following functions. This circuit
covers 8 lines corresponding to each extension, and 8 lines are
integrated into one Gate Array(IC101).
1. B channel communication / The B channel data are transferred between the DPT comm. Path
and the PCM highway. The transmitting capability is 64 kbps X2. / Note: B channel stands for
"Barer Channel", normally transmitting the voice data. / 2. D channel communication / The data
are transferred between the DPT comm. Path and the HDLC controller, serial bus. The
transmitting capability is 16 kbps. Because the communication between HDLC controller and
this circuit is done as 1 by 1, the HDLC controller switches the communication extension every
for 8 ms. / Therefore, the communication per one extension is done only 8 ms at 64 ms cycles,
the actual transmitting capability is 2 kbps. / Note: D channel stands for "Data Channel",
transmitting CPU control data. / 3. C channel communication / The serial/parallel data
conversion is done between the DPT comm. Path and the main CPU data bus. The level (H or L)
transmission is only possible through the C channel. / Note: C channel stands for "Control
Channel". /
(i) HDLC Controller / HDLC controller is a circuit which functions
the data format conversion of the D channel between the DPT
comm. line installed with a Gate Array (IC101) and the CPU data
bus by following the HDLC protocol. The serial/parallel
conversion is done at the same time. Though this circuit
communicates with 8 channel of the DPT comm. circuit, since it
can communicate only with one channel at a time, as before
mentioned it, switches the communicating extension every for 8
ms. /
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