Arrow BeMicro CV A9 Hardware Reference Manual page 13

FPGA Pin
Number
L7
K7
H8
G8
J7
J8
A10
A9
A8
A7
C6
D6
D7
C8
A5
B10
C9
B6
J9
H9
F14
E9
G11
J17
E12
D12
C11
K9
C13
D13
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Table 2-7: DDR3 pin assignments, signal names, and functions
Schematic Signal
Name
DDR3_A0 1.5V SSTL Class I
DDR3_A1 1.5V SSTL Class I
DDR3_A2 1.5V SSTL Class I
DDR3_A3 1.5V SSTL Class I
DDR3_A4 1.5V SSTL Class I
DDR3_A5 1.5V SSTL Class I
DDR3_A6 1.5V SSTL Class I
DDR3_A7 1.5V SSTL Class I
DDR3_A8 1.5V SSTL Class I
DDR3_A9 1.5V SSTL Class I
DDR3_A10 1.5V SSTL Class I
DDR3_A11 1.5V SSTL Class I
DDR3_A12 1.5V SSTL Class I
DDR3_A13 1.5V SSTL Class I
DDR3_BA0 1.5V SSTL Class I
DDR3_BA1 1.5V SSTL Class I
DDR3_BA2 1.5V SSTL Class I
DDR3_CASn 1.5V SSTL Class I
DDR3_CLK_P Differential 1.5-V SSTL Class I Clock
DDR3_CLK_N Differential 1.5-V SSTL Class I Clock
DDR3_CKE 1.5V SSTL Class I
DDR3_CSn 1.5V SSTL Class I
DDR3_DM0 1.5V SSTL Class I
DDR3_DM1 1.5V SSTL Class I
DDR3_DQ0 1.5V SSTL Class I
DDR3_DQ1 1.5V SSTL Class I
DDR3_DQ2 1.5V SSTL Class I
DDR3_DQ3 1.5V SSTL Class I
DDR3_DQ4 1.5V SSTL Class I
DDR3_DQ5 1.5V SSTL Class I
I/O Standard
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Bank address bus
Bank address Bus
Bank address bus
Column address strobe
Clock Enable
Chip Select
Data Mask
Data Mask
Data bus bit 0, byte lane 0
Data bus bit 1, byte lane 0
Data bus bit 2, byte lane 0
Data bus bit 3, byte lane 0
Data bus bit 4, byte lane 0
Data bus bit 5, byte lane 0
13
Description