Power Management Setup - QDI Pentium P5I430TX/IIB TITANIUM IIB Manual

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AWARD BIOS Description
Lat/RAS-to-CAS) &
SDRAM
Speculative Read
• System BIOS
Cacheable
• Video BIOS
Cacheable
• 8 Bit I/ O
Recovery Time
• 16 Bit I / O
Recovery Time
• Memory Hole At
15M-16M
• Pipeline Cache
Tim-Fastening
• Chipset NA#
Asserted
• Mem Drive Str.
(MA/RAS)
• DRAM Refresh
Rate

Power Management Setup

Power Management
PM Control by APM
Video Off Method
Video Off After
MODEM Use IRQ
3 - 8
configurations.
Other than conventional memory, the system BIOS
Enabled
area is also cacheable.
Disabled
The system BIOS area is not cacheable.
Enabled
Other than conventional memory, video BIOS area is
also cacheable.
Video BIOS area is not cacheable.
Disabled
It is the ISA Bus 8 bit I/O operating recovery time.
1∼ 4
NA
8 bit I/O recovery time does not exist.
It is the ISA Bus 16 bit I/O operating recovery time.
1∼ 4
16 bit I/O recovery time does not exist.
NA
Enabled
Memory Hole at 15-16M is reserved for expanded
PCI card..
Do not set this memory hole.
Disabled
This item allows you to select two timing of pipeline
Fastest
cache, faster and fastest.
Enabled
This item allows you to select between two methods
of chipset NA# asserted during CPU with cycles/CPU
Disabled
line fills Enabled or Disabled..
This item allows you select memory drive Str. If high
loading SIMM RAM is used (the number of memory
chips more than 64), you should select 16mA/16mA.
15.6us
For SDRAM and/or EDO/FPM memory subsystem..
For EDO/FPM only memory subsystem..
31.2us
64.4us
125us
Refresh disabled.
256us
Disabled
ROM PCI/ISA BIOS (2A59IQ1I)
POWER MANAGEMENT SETUP
AWARD SOFTWARE, INC.
: User Define
: Yes
IRQ [3-7, 9-15], NMI
: V/H SYNC + Blank
Primary IDE 0
: Standby
Primary IDE 1
: NA
Secondary IDE0
** Reload Global Timer Events **
: Enabled
: Disabled
: Disabled
: Disabled

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