Table of Contents
Advertisement
IC303 HD6433032SSNM11F
60
59 58 57
P7
/AN
61
2
2
P7
/AN
62
3
3
P7
/AN
63
4
4
P7
/AN
64
5
5
P7
/AN
65
6
6
P7
/AN
66
7
7
VREF
67
AVSS
68
P8
/IRQ
69
0
0
70
P8
/IRQ
1
1
71
P8
/IRQ
2
2
72
P8
/IRQ
3
3
PA
/TP
/TCLKA
73
0
0
PA
/TP
/TCLKB
74
1
1
75
PA
/TP
/TIOCA
/TCLKC
2
2
0
PA
/TP
/TIOCB
/TCLKD
76
3
3
0
77
PA
/TP
/TIOCA
4
4
1
PA
/TP
/TIOCB
78
5
5
1
PA
/TP
/TIOCA
79
6
6
2
80
PA
/TP
/TIOCB
7
7
2
IC304 SST29EE512-90-4C-NHTR
26
25
24
23
22
21 20 19 18
A8
27
A13
28
OE,CE,AND WE
29
A14
LOGIC
NC
30
WE
31
32
VCC
1
2
3
4
56 55 54 53 52 51 50 49 48 47 46 45 44
PORT 6
CLOCK
OSCILLATOR
ROM
(MASK ROM)
RAM
16 BIT
INTEGRATED
TIMER UNIT
(ITU)
PROGRAMMABLE
TIMING PATTERN
CONTROLLER
(TPC)
PORT B
1
2 3 4 5 6 7 8
17 16
15 14 13
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
CELL MATRIX
Y DECODER
X DECODER
5
6
7
8
9
10
11
12
43
42
41
PORT 5
ADDRESS BUS
DATA BUS (HIGH)
DATA BUS (LOW)
BUS
H8/300H CPU
CONTROLLER
INTERNUPTION
CONTROLLER
WATCH DOG TIMER
(WDT)
SERIAL COMMUNICATION
INTERFACE
(SCI) x 1CH
A/D CONVERTER
PORT 9
9 10 11 12
13 14 15 16 17 18 19 20
40
A
/P5
17
39
A
/P5
16
A
/P2
38
15
37
A
/P2
14
36
A
/P2
13
35
A
/P2
12
A
/P2
34
11
33
A
/P2
10
A
/P2
32
9
A
/P2
31
8
30
VSS
29
A
/P1
7
28
A
/P1
6
27
A
/P1
5
26
A
/P1
4
25
A
/P1
3
A
/P1
24
2
23
A
/P1
1
22
A
/P1
0
21
VCC
PORT 3
2
1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
79
Advertisement
Table of Contents
