System Structure; Acknowledge - Epson RTC-8564JE Applications Manual

RTC - 8564 JE/NB

8.3.5. System structure

A master is defined a device that controls interfacing of messages, and a slave is defined as a device which is
controlled by the master. A transmitter is defined as a device transmitting messages,and a receiver is defined as the
one receiving messages. In the case of the RTC-8564, controllers such as CPU are masters and the RTC-8564 is a
slave. Each device can be transmitter and receiver.
SDA
SCL

8.3.6. Acknowledge

There is no limit to the byte size of data transmitted between the start and stop conditions. For each byte during
interfacing, the receiver (receiving end) generates an acknowledge bit to the transmitter (sending end) to confirm that
it has received the data. Because the acknowledge bit is LOW active, the transmitter sets the SDA line to HIGH, and
sends out a clock pulse for the acknowledge bit. If the receiver can correctly receive the 8-bit data from the transmitter,
it will set the SDA line to LOW when the clock for the last bit is finished. Because the I
SDA line of transmitter also turns to LOW. At this moment, the transmitter checks that the acknowledge has returned,
and then continues to send out the next data. When the clock pulse for the acknowledge bit is finished, the receiver
turns the SDA line to HIGH (release) and prepares to receive the next data.
When a master device is acting as a transmitter and acknowledge is confirmed from the receiver, if the next data is not
sent/received but the stop condition is generated, it is possible to terminate the communication normally. When a
master device is acting as a receiver and acknowledge bit is sent out as "1", it is possible to terminate the
communication normally if the stop condition is generated.
Master Slave
Transmitter Transmitter
/ Receiver / Receiver
CPU etc. RTC - 8564
Master
Transmitter
/ Receiver
Page - 9
Slave
Transmitter
/ Receiver
Other PC-BUS devices
2
C-BUS lines are pulled-up, the
MQ - 322 - 04