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RTC - 8564 JE/NB
2
8.3.7. I
C-BUS protocol
The following section describes the communications procedure where the master is CPU and the slave is the
RTC-8564.
(1) Procedure for write at specified address
The RTC-8564 has an auto increment function of address. After the initial address is set, if only data continues
to be sent, the receiving address on the 8564 is incremented by 1 byte. The procedure as follows:
(1) The CPU sends out a start condition.
(2) The CPU sends out the slave address of the 8564 and the R/W bit, in write mode.
(3) Confirm acknowledge from the 8564.
(4) The CPU sends out the write address to the 8564.
(5) Confirm acknowledge from the 8564.
(6) The CPU sends out the data for write to the address specified in step (4).
(7) Confirm acknowledge from the 8564.
(8) If necessary repeat steps (6) and (7). The address will be automatically incremented internally on the 8564.
(9) The CPU sends out the stop condition.
(1)
(2)
S
Slave address
(2) Procedure for read at specified address
According to the write mode, after the address to read is written, the read mode is set and the actual data read.
The procedure as follows:
(1) The CPU sends out a start condition.
(2) The CPU sends out the slave address of the 8564 and the R/W bit, in write mode.
(3) Confirm acknowledge from the 8564.
(4) The CPU sends out the address read out from the 8564.
(5) Confirm acknowledge from the 8564.
(6) The CPU sends out the start condition (stop condition is not sent.)
(7) The CPU sends out the slave address of the 8564 and the R/W bit, in read mode.
(8)
Confirm acknowledge from the 8564.(From here on, the CPU acts as a receiver and the 8564 as a
transmitter.)
(9) Data at the address specified in step (4) is sent out from the 8564.
(10) The CPU sends out acknowledge to the 8564.
(11) If necessary repeat steps (9) and (10). The read address will be automatically incremented internally on
the 8564.
(12) The CPU sends out the stop condition.
(1)
(2)
S
Slave address
(3) Read procedure without specified address
Immediately after the read mode is set up, data can be read. In this case, the address is the address when the
previous access ended, plus 1. The procedure is as follows:
(1) The CPU sends out a start condition.
(2) The CPU sends out the slave address of the 8564 and the R/W bit, in read mode.
(3) Confirm acknowledge from the 8564.(From here on, the CPU acts as a receiver and the 8564 as a
transmitter.)
(4) Data at the last address in the previous access plus 1 is sent out from the 8564.
(5) The CPU sends out acknowledge to the 8564.
(6) If necessary repeat steps (4) and (5). The read address will be automatically incremented internally on the
8564.
(7) The CPU sends out acknowledge of "1".
(8) The CPU sends out the stop condition.
(1)
(2)
S
Slave address
(3)
(4)
(5)
0
0
Address
0
R/W
Acknowledge from the 8564
(3)
(4)
(5)
0
0
Address
0
R/W
Acknowledge from the 8564
(3)
(4)
(5)
1
0
Data
0
R/W
Acknowledge from the 8564
Page - 10
(6)
(7)
Data
0
Data
(6)
(7)
(8)
S
Slave address
1
0
R/W
(6)
(7)
(8)
Data
1
P
Acknowledge from the CPU
(8)
(9)
0
P
(9)
(10)
(11)
Data
0
Data
Acknowledge from the CPU
MQ - 322 - 04
(12)
(13)
1
P
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