Co1 Counter Add-On; Hardware - Jäger ADwin-Gold-USB Manual

ADwin

8 CO1 Counter Add-On

The technical data of the counter add-on CO1 is described in the annex A.1.

8.1 Hardware

The counter add-on CO1 (ordering option Gold-CO1) has four 32-bit up/down
counters with four-edge-evaluation. You can configure and read out the
counters individually as well as all together. (The block diagram shows the
design of a single counter).
The counters can be internally or externally clocked and are read out via
accompanying latches. All counters have each a Latch A and a Latch B. The
counter values can be cleared or transferred in a latch by using programming
commands or (if configured) when there is an external signal at CLR/LATCH.
A / CLK
A / CLK
B / DIR
B / DIR
CLR / LATCH
CLR / LATCH
A / CLK 4k7
B / DIR 4k7
CLR / LATCH 4k7
There are the following operating modes: event counting (external clock) and
pulse width measurement (internal clock); see also chapter 8.3 / 8.4:
a) Event counting: Incrementing/decrementing of the counter is caused by
external square-wave signals at the inputs A/CLK and B/DIR. A positive
edge at CLR/LATCH either sets the counter to zero (CLR) or copies the
counter values into the latch (LATCH).
The following modes are possible:
1. Clock and direction: A positive edge at CLK increments or decrements
the counter values by one. The signal at DIR determines the counting
direction (0 = decrement; 1 = increment).
2. Four edge evaluation: Every edge of the signals (phase-shifted by 90
degrees) at A/CLK and B/DIR causes the counter to increment/decre-
ment. The counting direction is determined by the sequence of the ris-
ing/falling edges of these signals. This mode is particularly used for
quadrature encoders.
b) Pulse width measurement: Incrementing/decrementing of the counter is
caused by an internal reference clock generator; a signal frequency of 5
MHz or 20 MHz can be used. The square-wave signal at CLR/LATCH is
evaluated: With every positive edge the counter values are written to latch
A, with a negative edge to latch B.
ADwin-Gold USB / ENET, manual version 3.8, October 2005
ref.-CLK
G
20 MHz
4-edge
evaluation
DIR
Fig. 16 – Block diagram of the Gold-CO1 counter add-on
Divider
to f -switch of
÷ 4 ref
other counters
Up
CO1 Counter Add-On
Counter
Latch A and B
32 bit Latch A
Data
CLK
DIR
32 bit Counter
CLR
EN
32 bit Latch B
Data
Control Registers
Data
External clock input
Internal clock input
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