Detail Description - OCI BDL800IR Instruction Manual

A lock-in amplifier for phase sensitive detection is built into this unit. It consists of one
phase-locked loop (PLL), one phase sensitive detector (PSD), two single-ended analog-to-
digital converters (ADC), and two digital-to-analog converters (DAC). Also available are
four lines for digital input and four lines for digital output. The PLL can be set to lock either
on the fundamental or the second harmonic.
Sensitivity, time constant, and phase are controlled externally by the AES software. The
phase can be adjusted to 90° or 180°.
4.2.1

Detail Description

High Voltage Ramp Generator
Sweep Generator
Internal Oscillator and
Modulator
PSD
18 Chapter 4 Electronics
Sweep Voltage
Sweep Rate
Sweep Voltage Offset
(start)
Sweep Voltage Offset
(end)
Ramp Voltage Moni-
tor
Frequency
Amplitude (peak-to-
peak)
Distortion
Type
Input Impedance
Input
AC Gain
Interstage Coupling
Post Detection Low
Pass Filter
Signal Channel
Equivalent Input
0–2000 V
AES software controlled (16-bit DAC)
AES software controlled (16-bit DAC)
AES software controlled (16-bit DAC)
AES software controlled (16-bit DAC)
Fixed at 1.457 kHz, trimmer adjusted ±5%
Regulated from 0.5 to 20 V (16-bit DAC)
Harmonic 0.1%
Noise 50 μV RMS
Switching multiplier
AC coupled, 100 nF into 1 MΩ
True differential
10, 100, 1000, 10000 (and 1, 2, 4, 8) software
selectable
Simple high pass typically with 3 dB per
72 Hz
Equal component Sallen-Key, 2
a time constant of 0.1, 0.5, 1, and 3 s
Typically less than 20 nV/Hz at 1 kHz
nd
order with