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6. External View
LVDS I/O Connect P.27
PLL Setting DipSW P.14
LVDS I/O Power Setting P.11
RS-232C Port P.17
User PushSW P.15
Virtex5 FPGA
DDR2 SDRAM SO-DIMM Socket P.18
Option I/O Power Setting P.9
PC4 Connect P.56
JTAG Pin Header P.56
Config Mode Setting P.68
Option I/O Connect P.31
7. Board Specification
Out side dimension
Board Layer
Thickness
Board Material
FPGA
Configuration
DDR2 SDRAM chip
Memory Module
LVDS I/O
High speed I/O
Multi-purpose I/O
Soft-touch connector
10/100 Base Ethernet
RS232C
4, 2007 (Rev 2.1s)
Sep
TB-5V-LX110/220/330-DDR2Hardware User Guide Rev2.1s
VBATT_0 Level Setting P.54
Soft Tough Connect P.41
Program LED P.51
Figure.2 TB-5V-LX110/220/330-DDR2 board outline
: 250mm x 230mm
: 12 Layers
: 1.6mm
: General FR4
: XC5VLX110 or 220 or 330-1FF1760C
: TE7725PF (TED) and Flash memory: S29G128N(Spansion)
: EDE5116AHSE (32Mbit X 16 ELPIDA) 3 chips
: DDR2 SDRAM SO-DIMM Socket (Up to 2GB)
: 56 pins connector (I/O:22 pair) Tx, Rx
: 100 pins connector (I/O: 42 pins) x4
: 30 pins Pin-header (I/O: 20 pins) x1
: Soft-touch probe x5 (Agilent Technology)
: RJ45 modular Jack
: Interface with PC
OSC Socket P.13
Flash Memory Area Setting SW P.52
6/26
10/100 Base Ethernet P.25
General I/O Pin Header P.40
User DipSW P.15
User LED
Power SW
Power Status LED 1.0V P.8
Power Status LED 1.8V P.8
Power Status LED 0.9V P.8
DDR2 SDRAM Memory P.21
Power Status LED 3.3V P.8
Power Status LED 2.5V P.8
Config SW P.69
PC4 Connect P.56
JTAG Pin Header P.56
Config Setting SW P.51
Option I/O Connect P.31
Soft Tough Connect P.41
P.16
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