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TB-KU-060/075-ACDC8K
Inrevium TB-KU-060/075-ACDC8K Manuals
Manuals and User Guides for Inrevium TB-KU-060/075-ACDC8K. We have
1
Inrevium TB-KU-060/075-ACDC8K manual available for free PDF download: Hardware User Manual
Inrevium TB-KU-060/075-ACDC8K Hardware User Manual (89 pages)
TB-KU-xxx-ACDC8K series
Brand:
Inrevium
| Category:
Motherboard
| Size: 4 MB
Table of Contents
Table of Contents
3
1 Related Documents and Accessories
9
2 Overview
9
3 Feature
10
4 Block Diagram
11
Figure 4-1 Block Diagram
11
5 External View of the Board
12
Figure 5-1 Board Top View
12
6 Board Specifications
13
Figure 6-1 Board Dimensions (Inclusive of Wastable Substrate, Top View)
14
Figure 6-2 Board Dimensions (Inclusive of Wastable Substrate, Bottom View)
15
7 Description of Components
16
Power Supply Structure
16
Figure 7-1 Power Supply Structure
16
Figure 7-2 Power Sequencer
17
Figure 7-3 Power Input Circuit
17
Power Input Connectors
17
Power Sequencing
17
DC 4-Pin Header and Binding Posts
18
Figure 7-4 12VDC Input Connector and Binding Posts
18
Table 7-1 Voltage Rails Test Points
19
Voltage Rails Test Points
19
Power and Miscellaneous Leds
20
Table 7-2 Board Leds
20
Board Power Button
21
Figure 7-5 Board Power Button
21
FPGA HR Bank Voltage Selection
21
HR Banks Voltage and SFP+ RX_LOS/TX_FAULT Selection
21
Table 7-3 HR Banks Connected Peripherals
21
Table 7-4 HR Banks Voltage and RX_LOS/TX_FAULT Selection
21
FPGA Banks Assignments
22
Figure 7-6 FPGA Banks Assignments
22
Clock System
23
VCCINT Clock Architecture
23
Figure 7-7 VCCINT Clock Synchronization
23
GTH Clocks
24
Figure 7-8 GTH and MMCX Clocks Architecture
24
User Assigned Clocks
25
Figure 7-9 User Assigned Clocks Architecture
25
FMC Connector Interface
26
Fmc Hpc 0 (J1)
26
Figure 7-10 High Pin Count FMC
26
Table 7-5 FMC 0 (J1) to FPGA Pinout
27
Figure 7-11 FMC 0 to 6 SCL/SDA, GA0/GA1, TDI/TDO
32
Fmc Hpc 1 (J2)
34
Table 7-6 FMC 1 (J2) to FPGA Pinout
35
Fmc Hpc 2 (J5)
41
Table 7-7 FMC 2 (J5) to FPGA Pinout
42
Fmc Hpc 3 (J8)
48
Table 7-8 FMC 3 (J8) to FPGA Pinout
49
Fmc Hpc 4 (J11)
55
Table 7-9 FMC 4 (J11) to FPGA Pinout
56
Fmc Hpc 5 (J14)
62
Table 7-10 FMC 5 (J14) to FPGA Pinout
63
Fmc Hpc 6 (J19)
69
Table 7-11 FMC 6 (J19) to FPGA Pinout
70
Ddr4 Sdram
76
Figure 7-12 DDR4 SDRAM Structure
76
SFP+ Connectors
77
Figure 7-13 I2C MUX Hardware-Selectable Address Pins
77
Table 7-12 SFP+ I2C Bus Pin Assignment
78
Table 7-13 RX_LOS, TX_FAULT and RS Pin Assignment
78
USB to UART Controller
79
Figure 7-14 USB UART Interface
79
Table 7-14 Micro-USB Type B and AB Compatibility
79
Table 7-15 UART Interface Pin Assignment
79
Battery
80
Figure 7-15 Battery Circuit
80
Dual Quad (X8) SPI Flash
81
Figure 7-16 FPGA SPI Flash Configuration Structure
81
JTAG and Pmod Interface
82
JTAG Connector
82
Table 7-16 SPI Flash Memory Pin Assignment
82
Table 7-17 Xilinx 14-Pin JTAG Pinout
82
Table 7-18 FPGA Bank 0 JTAG Pin Assignment
82
Pmod Interface
83
Figure 7-17 Pmod Connection
83
Table 7-19 Pmod Pin Assignment
83
General Purpose Leds
84
Table 7-20 Uncommitted Leds Pin Assignment
84
General Purpose Switches
85
DIP Switches
85
Push Switches
85
Table 7-21 DIP Switches Pin Assignment
85
Table 7-22 Push-Button Switches Pin Assignment
85
Jumper Switches
86
Figure 7-18 Jumper Switches Structure
86
Table 7-23 Jumper Switches Pin Assignment
86
8 Appendix
87
Default Settings
87
Figure 8-1 Jumper and Switch Location (Component Side)
87
Power Sequencer Timings
88
Figure 8-2 Power Sequencer Default Settings
88
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