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Inrevium TB-KU-060/075-ACDC8K Hardware User Manual

Tb-ku-xxx-acdc8k series
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TB-KU-xxx-ACDC8K Hardware User Manual
TB-KU-xxx-ACDC8K
Hardware User Manual
Rev. 1.03
1
Rev. 1.03

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Summary of Contents for Inrevium TB-KU-060/075-ACDC8K

  • Page 1 TB-KU-xxx-ACDC8K Hardware User Manual TB-KU-xxx-ACDC8K Hardware User Manual Rev. 1.03 Rev. 1.03...
  • Page 2 TB-KU-xxx-ACDC8K Hardware User Manual Revision History Version Date Description Publisher Rev. 1.00 2014/10/15 Initial Release Rev. 1.01 2015/01/19 Updated content with board pictures and FMC pinout tables Rev. 1.02 2015/02/18 Updated Figure 4-1, 7-2, 7-6, 7-16 Rev. 1.03 2015/07/21 Released for 060 Morita Added Standoffs and Power Strip cord Odajima...

  • Page 3: Table Of Contents

    TB-KU-xxx-ACDC8K Hardware User Manual Table of Contents Related Documents and Accessories ..................9 Overview ............................9 Feature ............................10 Block Diagram ..........................11 External View of the Board ......................12 Board Specifications ........................13 Description of Components ....................... 16 7.1. Power Supply Structure ......................
  • Page 4 TB-KU-xxx-ACDC8K Hardware User Manual List of Figures Figure 4-1 Block Diagram ......................... 11 Figure 5-1 Board Top View ....................... 12 Figure 6-1 Board Dimensions (inclusive of wastable substrate, top view) ........14 Figure 6-2 Board Dimensions (inclusive of wastable substrate, bottom view) ......... 15 Figure 7-1 Power Supply Structure ....................
  • Page 5 TB-KU-xxx-ACDC8K Hardware User Manual List of Tables Table 7-1 Voltage Rails Test Points ....................19 Table 7-2 Board LEDs ........................20 Table 7-3 HR Banks Connected Peripherals ................... 21 Table 7-4 HR Banks Voltage and RX_LOS/TX_FAULT Selection ........... 21 Table 7-5 FMC 0 (J1) to FPGA Pinout ....................27 Table 7-6 FMC 1 (J2) to FPGA Pinout ....................
  • Page 6 TB-KU-xxx-ACDC8K Hardware User Manual Introduction Thank you for purchasing the TB-KU-xxx-ACDC8K board. Before using the product, be sure to carefully read this user manual and fully understand how to correctly use the product. First read through this manual, and always keep it handy. SAFETY PRECAUTIONS Be sure to follow these precautions Observe the precautions listed below to prevent injuries to you or other personnel or damage to property.
  • Page 7 TB-KU-xxx-ACDC8K Hardware User Manual Warning In the event of a failure, disconnect the power supply. If the product is used as is, a fire or electric shock may occur. Disconnect the power supply immediately and contact our sales personnel for repair. If an unpleasant smell or smoking occurs, disconnect the power supply.
  • Page 8 TB-KU-xxx-ACDC8K Hardware User Manual Caution Do not use or place the product in the following locations.  Humid and dusty locations  Airless locations such as closet or bookshelf  Locations which receive oily smoke or steam  Locations exposed to direct sunlight ...

  • Page 9: Related Documents And Accessories

    TB-KU-xxx-ACDC8K Hardware User Manual 1. Related Documents and Accessories Related documents: All documents relating to this board can be downloaded from our website. Please see attached paper on the products. Xilinx FPGA document: http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/kintex-ultras cale.html DS892: UltraScale device data sheets: Kintex UltraScale Architecture Data Sheet: DC and AC Switching Characteristics DS890: UltraScale Architecture and Product Overview UG570: UltraScale Architecture Configuration User Guide...

  • Page 10: Feature

    TB-KU-xxx-ACDC8K Hardware User Manual 3. Feature Xilinx Kintex UltraScale: XCKU060/XCKU085 -2 speed grade in FFVA1517 package Memory: 4GByte DDR4 SDRAM: 16Gbits (4 ICs x 32M words x 16 bits x 8 banks) x 2 banks of ICs 256Mbit Dual Quad SPI Flash TI’s UCD9090 power supply sequencer and monitor 7 x Samtec’s ASP-134486-01 FMC Connector:...

  • Page 11: Block Diagram

    TB-KU-xxx-ACDC8K Hardware User Manual 4. Block Diagram The following figure shows the block diagram of TB-KU-xxx-ACDC8K FMC0 does not have any high-speed GTH lanes. XCKU060: FMC1, 2 and 3 have 8 high-speed GTH lanes. FMC4 and 6 have 4 high-speed GTH lanes. FMC5 and SFP+ do not have any high-speed GTH lanes.

  • Page 12: External View Of The Board

    TB-KU-xxx-ACDC8K Hardware User Manual 5. External View of the Board The TB-KU-xxx-ACDC8K board’s components are shown on the top side view in Figure 5-1. GTH CLK FMC Connector 6 (HPC) Sequencer HR Voltage MMCX Inputs PMBUS Header Select Header LA Group B (6pairs) 12V Input Dual Quad GTH 4Lanes...

  • Page 13: Board Specifications

    TB-KU-xxx-ACDC8K Hardware User Manual 6. Board Specifications Figure 6-1 shows the board specifications. External Dimensions: 313.08 mm (W) x 208.28 mm (H) Number of Layers: 20 layers Board Thickness: 2.0828 mm +/- 10% Material: Megtron 4 FPGA: Xilinx Kintex UltraScale XCKU060/XCKU085 FFVA1517 (FLVA1517) package FMC HPC CC Connector: Samtec ASP-134486-01 Micro-USB Connector:...

  • Page 14: Figure 6-1 Board Dimensions (Inclusive Of Wastable Substrate, Top View)

    TB-KU-xxx-ACDC8K Hardware User Manual Figure 6-1 Board Dimensions (inclusive of wastable substrate, top view) Rev. 1.03...

  • Page 15: Figure 6-2 Board Dimensions (Inclusive Of Wastable Substrate, Bottom View)

    TB-KU-xxx-ACDC8K Hardware User Manual Figure 6-2 Board Dimensions (inclusive of wastable substrate, bottom view) Rev. 1.03...

  • Page 16: Description Of Components

    TB-KU-xxx-ACDC8K Hardware User Manual 7. Description of Components 7.1. Power Supply Structure TB-KU-xxx-ACDC8K board’s power supply structure is shown in the figure below. KCU Vccint 0.95V +/- 3% (0.922 to Fuse 0.979V)=41.6A LMZ31710 x 6 KCU Vccint_io 0.95V +/- 3%=2.6A from Sequencer 60A current share Total 44.2A...

  • Page 17: Power Sequencing

    TB-KU-xxx-ACDC8K Hardware User Manual 7.1.1. Power Sequencing The UCD9090 chip features power sequencing and monitoring of the different power supplies available on this board. The sequencer’s outputs are connected to the power supplies’ enable pin which activates each device. UCD9090RGZ 12V0 MON1 GPIO1...

  • Page 18: Dc 4-Pin Header And Binding Posts

    TB-KU-xxx-ACDC8K Hardware User Manual 7.1.3. DC 4-pin Header and Binding Posts Important: There are two (2) power inputs available on this board. Connect one OR the other 12VDC inputs. NEVER connect both power inputs simultaneously. Figure 7-4 12VDC Input Connector and Binding Posts Rev.

  • Page 19: Voltage Rails Test Points

    TB-KU-xxx-ACDC8K Hardware User Manual 7.1.4. Voltage Rails Test Points Use the development board’s power rail test points for board debugging and troubleshooting or for other types of measurements. Table 7-1 Voltage Rails Test Points Voltage Rail Test Point # Power Supply for 0V95 TP37 FPGA VCCINT...

  • Page 20: Power And Miscellaneous Leds

    TB-KU-xxx-ACDC8K Hardware User Manual 7.1.5. Power and Miscellaneous LEDs Shown below are the different LEDs present on the board which serve as power indication or general purpose programmable LEDs. Table 7-2 Board LEDs Color Used for FPGA Programming DONE signal Bicolor: Red: Programming in progress Green or Red...

  • Page 21: Board Power Button

    TB-KU-xxx-ACDC8K Hardware User Manual 7.1.6. Board Power Button This board features a power button rocker switch on the chassis’ front panel along with 4 SFP+ connectors, a micro USB port and a green and red LED to signal the FPGA programming and idle states. The power sequencer monitors the rocker switch power button which disables power supplies on the board when turned off.

  • Page 22: Fpga Banks Assignments

    TB-KU-xxx-ACDC8K Hardware User Manual 7.2. FPGA Banks Assignments This board supports Xilinx Kintex Ultrascale XCKU060 and XCKU085 FPGA in the FFVA1517 (FLVA1517) packages. The figure below presents bank assignments on this board. FMC6 FMC4 (4Lane) (4Lane) FMC3 FMC2 (8Lane) (8Lane) FMC1 (8Lane) GTH Total 32CH...

  • Page 23: Clock System

    TB-KU-xxx-ACDC8K Hardware User Manual 7.3. Clock System 7.3.1. VCCINT Clock Architecture The diagram below represents the clocking architecture of 6 - LMZ31710 modules interconnected to provide 60A output current sharing for the FPGA. The LTC6909 chip provides phase synchronized outputs with 60° offsets. LMZ31710 LMZ31710 LMZ31710...

  • Page 24: Gth Clocks

    TB-KU-xxx-ACDC8K Hardware User Manual 7.3.2. GTH Clocks The diagram below represents the GTH clock architecture present in the TB-KU-xxx-ACDC8K board. Some clocks are internally driven by the system while others can be externally provided through MMCX connectors. DIP-SW: SW2 【DIP-SW : OFF】 156.25MHz (LVDS) Quad232(085 Only) CLK_GLOBAL_SEL: 0...

  • Page 25: User Assigned Clocks

    TB-KU-xxx-ACDC8K Hardware User Manual 7.3.3. User Assigned Clocks This board provides a way to make use of dedicated LA signals on the FMC cards allowing them to be configured as global clocks on the FPGA as shown in the figure below. The figure states the GC and GBC clock assignments on the FPGA for the FMCs and the DDR4 banks.

  • Page 26: Fmc Connector Interface

    TB-KU-xxx-ACDC8K Hardware User Manual 7.4. FMC Connector Interface The TB-KU-xxx-ACDC8K board has 7 high-pin count (HPC) 400 pin FMC connectors (FMC 0 to 6) on board as shown on the block diagram. These FMC connectors follow the VITA 57.1 standard with Samtec ASP-134486-01 connectors.

  • Page 27: Table 7-5 Fmc 0 (J1) To Fpga Pinout

    TB-KU-xxx-ACDC8K Hardware User Manual Table 7-5 FMC 0 (J1) to FPGA Pinout Bank# Pin# Pin# Bank# CLK_DIR DP1_M2C_P DP1_M2C_N DP9_M2C_P DP9_M2C_N DP2_M2C_P DP2_M2C_N DP8_M2C_P DP8_M2C_N DP3_M2C_P DP3_M2C_N DP7_M2C_P DP7_M2C_N DP4_M2C_P DP4_M2C_N DP6_M2C_P DP6_M2C_N DP5_M2C_P DP5_M2C_N *1 GBTCLK1_M2C_P *1 GBTCLK1_M2C_N DP1_C2M_P DP1_C2M_N DP9_C2M_P DP9_C2M_N...
  • Page 28 TB-KU-xxx-ACDC8K Hardware User Manual FMC 0 (J1) Bank# Pin# Pin# Bank# *5 PG_C2M DP0_C2M_P DP0_C2M_N *1 GBTCLK0_M2C_P *1 GBTCLK0_M2C_N DP0_M2C_P DP0_M2C_N LA01_P_CC AL14 LA01_N_CC AL13 AU12 LA06_P AV12 LA06_N LA05_P AV13 LA05_N AW13 AJ16 LA10_P LA09_P AK13 AK16 LA10_N LA09_N AK12 LA13_P AK18...
  • Page 29 TB-KU-xxx-ACDC8K Hardware User Manual FMC 0 (J1) Bank# Pin# Pin# Bank# *5 PG_M2C AD14 HA01_P_CC AD13 HA01_N_CC HA00_P_CC AE12 HA00_N_CC AF12 AE18 HA05_P AF18 HA05_N HA04_P AP15 HA04_N AR15 HA09_P HA09_N HA08_P HA08_N HA13_P HA13_N HA12_P HA12_N HA16_P HA16_N HA15_P HA15_N HA20_P HA20_N...
  • Page 30 TB-KU-xxx-ACDC8K Hardware User Manual FMC 0 (J1) Bank# Pin# Pin# Bank# *7 VREF_A_M2C AL12 CLK1_M2C_P *5 PRSNT_M2C_L AM12 CLK1_M2C_N CLK0_M2C_P AM14 CLK0_M2C_N AN14 AN13 LA00_P_CC AN12 LA00_N_CC LA02_P AR12 LA02_N AT12 AR13 LA03_P AT13 LA03_N LA04_P AT14 LA04_N AU14 AV14 LA08_P AW14 LA08_N...
  • Page 31 TB-KU-xxx-ACDC8K Hardware User Manual FMC 0 (J1) Bank# Pin# Pin# Bank# *7 VREF_B_M2C CLK3_M2C_P CLK3_M2C_N CLK2_M2C_P CLK2_M2C_N AD16 HA03_P AE16 HA03_N HA02_P AG17 HA02_N AG16 HA07_P HA07_N HA06_P HA06_N HA11_P HA11_N HA10_P HA10_N HA14_P HA14_N HA17_P_CC HA17_N_CC HA18_P HA18_N HA21_P HA21_N HA22_P HA22_N...

  • Page 32: Figure 7-11 Fmc 0 To 6 Scl/Sda, Ga0/Ga1, Tdi/Tdo

    TB-KU-xxx-ACDC8K Hardware User Manual Figure 7-11 FMC 0 to 6 SCL/SDA, GA0/GA1, TDI/TDO Note: The above structure is identical for all FMC connectors on this board, with the exception of test points and reference designators being different per FMC. Rev. 1.03...
  • Page 33 TB-KU-xxx-ACDC8K Hardware User Manual For FMC 0 (J1): *1: There are no GTH channels on this connector so the GBTCLK1_M2C_P/N signals are not connected. *2: SCL, SDA The board provides test points with pull-up options to enable I2C communication with the FPGA. By default, the pull-ups are not populated.

  • Page 34: Fmc Hpc 1 (J2)

    TB-KU-xxx-ACDC8K Hardware User Manual 7.4.2. FMC HPC 1 (J2) This FMC connects GTH lanes and all of the available LA signals to banks on the FPGA. High Speed: Quad 224 and 225:  8 GTH lanes  2 differential clock pairs Low Speed: Bank 44: ...

  • Page 35: Table 7-6 Fmc 1 (J2) To Fpga Pinout

    TB-KU-xxx-ACDC8K Hardware User Manual Table 7-6 FMC 1 (J2) to FPGA Pinout Bank# Pin# Pin# Bank# CLK_DIR DP1_M2C_P DP1_M2C_N DP9_M2C_P DP9_M2C_N DP2_M2C_P DP2_M2C_N DP8_M2C_P DP8_M2C_N DP3_M2C_P DP3_M2C_N DP7_M2C_P DP7_M2C_N DP4_M2C_P DP4_M2C_N DP6_M2C_P DP6_M2C_N DP5_M2C_P DP5_M2C_N *1 GBTCLK1_M2C_P AP10 *1 GBTCLK1_M2C_N DP1_C2M_P DP1_C2M_N DP9_C2M_P...
  • Page 36 TB-KU-xxx-ACDC8K Hardware User Manual FMC 1 (J2) Bank# Pin# Pin# Bank# *5 PG_C2M DP0_C2M_P DP0_C2M_N *1 GBTCLK0_M2C_P AT10 *1 GBTCLK0_M2C_N DP0_M2C_P DP0_M2C_N LA01_P_CC AM22 LA01_N_CC AN22 AR22 LA06_P AR23 LA06_N LA05_P AT22 LA05_N AU22 AW25 LA10_P LA09_P AV23 AW26 LA10_N LA09_N AW23 LA13_P...
  • Page 37 TB-KU-xxx-ACDC8K Hardware User Manual FMC 1 (J2) Bank# Pin# Pin# Bank# *5 PG_M2C HA01_P_CC HA01_N_CC HA00_P_CC HA00_N_CC HA05_P HA05_N HA04_P HA04_N HA09_P HA09_N HA08_P HA08_N HA13_P HA13_N HA12_P HA12_N HA16_P HA16_N HA15_P HA15_N HA20_P HA20_N HA19_P HA19_N HB03_P HB03_N HB02_P HB02_N HB05_P HB05_N...
  • Page 38 TB-KU-xxx-ACDC8K Hardware User Manual FMC 1 (J2) Bank# Pin# Pin# Bank# *7 VREF_A_M2C AK22 CLK1_M2C_P *5 PRSNT_M2C_L AL22 CLK1_M2C_N CLK0_M2C_P AK23 CLK0_M2C_N AL23 AM21 LA00_P_CC AN21 LA00_N_CC LA02_P AJ20 LA02_N AJ21 AP21 LA03_P AR21 LA03_N LA04_P AH22 LA04_N AH23 AV21 LA08_P AW21 LA08_N...
  • Page 39 TB-KU-xxx-ACDC8K Hardware User Manual FMC 1 (J2) Bank# Pin# Pin# Bank# *7 VREF_B_M2C CLK3_M2C_P CLK3_M2C_N CLK2_M2C_P CLK2_M2C_N HA03_P HA03_N HA02_P HA02_N HA07_P HA07_N HA06_P HA06_N HA11_P HA11_N HA10_P HA10_N HA14_P HA14_N HA17_P_CC HA17_N_CC HA18_P HA18_N HA21_P HA21_N HA22_P HA22_N HA23_P HA23_N HB01_P HB01_N...
  • Page 40 TB-KU-xxx-ACDC8K Hardware User Manual For FMC 1 (J2): *1: GBTCLK[0:1]_M2C_P/N These clocks are connected to Quad 224 of the FPGA while this board provides an MMCX interface for one pair of clocks on Quad 225. The other pair is provided by the system clock buffer. *2: SCL, SDA The board provides test points with pull-up options to enable I2C communication with the FPGA.

  • Page 41: Fmc Hpc 2 (J5)

    TB-KU-xxx-ACDC8K Hardware User Manual 7.4.3. FMC HPC 2 (J5) This FMC connects GTH lanes and 6 differential pairs of LA signals to banks on the FPGA. High Speed: Quad 226 and 227:  8 GTH lanes  2 differential clock pairs Low Speed: Bank 25: ...

  • Page 42: Table 7-7 Fmc 2 (J5) To Fpga Pinout

    TB-KU-xxx-ACDC8K Hardware User Manual Table 7-7 FMC 2 (J5) to FPGA Pinout Bank# Pin# Pin# Bank# CLK_DIR DP1_M2C_P DP1_M2C_N DP9_M2C_P DP9_M2C_N DP2_M2C_P DP2_M2C_N DP8_M2C_P DP8_M2C_N DP3_M2C_P DP3_M2C_N DP7_M2C_P DP7_M2C_N DP4_M2C_P DP4_M2C_N DP6_M2C_P DP6_M2C_N DP5_M2C_P DP5_M2C_N *1 GBTCLK1_M2C_P AF10 *1 GBTCLK1_M2C_N DP1_C2M_P DP1_C2M_N DP9_C2M_P...
  • Page 43 TB-KU-xxx-ACDC8K Hardware User Manual FMC 2 (J5) Bank# Pin# Pin# Bank# *5 PG_C2M DP0_C2M_P DP0_C2M_N *1 GBTCLK0_M2C_P AH10 *1 GBTCLK0_M2C_N DP0_M2C_P DP0_M2C_N LA01_P_CC LA01_N_CC LA06_P LA06_N LA05_P LA05_N LA10_P LA09_P LA10_N LA09_N LA13_P LA14_P LA13_N LA14_N LA17_P_CC LA17_N_CC LA18_P_CC LA18_N_CC LA23_P LA23_N LA27_P...
  • Page 44 TB-KU-xxx-ACDC8K Hardware User Manual FMC 2 (J5) Bank# Pin# Pin# Bank# *5 PG_M2C HA01_P_CC HA01_N_CC HA00_P_CC HA00_N_CC HA05_P HA05_N HA04_P HA04_N HA09_P HA09_N HA08_P HA08_N HA13_P HA13_N HA12_P HA12_N HA16_P HA16_N HA15_P HA15_N HA20_P HA20_N HA19_P HA19_N HB03_P HB03_N HB02_P HB02_N HB05_P HB05_N...
  • Page 45 TB-KU-xxx-ACDC8K Hardware User Manual FMC 2 (J5) Bank# Pin# Pin# Bank# *7 VREF_A_M2C CLK1_M2C_P *5 PRSNT_M2C_L CLK1_M2C_N CLK0_M2C_P CLK0_M2C_N AW33 LA00_P_CC AW34 LA00_N_CC LA02_P LA02_N AR33 LA03_P AT33 LA03_N LA04_P LA04_N AT34 LA08_P AU34 LA08_N LA07_P LA07_N AV33 LA12_P AV34 LA12_N LA11_P LA11_N...
  • Page 46 TB-KU-xxx-ACDC8K Hardware User Manual FMC 2 (J5) Bank# Pin# Pin# Bank# *7 VREF_B_M2C CLK3_M2C_P CLK3_M2C_N CLK2_M2C_P CLK2_M2C_N HA03_P HA03_N HA02_P HA02_N HA07_P HA07_N HA06_P HA06_N HA11_P HA11_N HA10_P HA10_N HA14_P HA14_N HA17_P_CC HA17_N_CC HA18_P HA18_N HA21_P HA21_N HA22_P HA22_N HA23_P HA23_N HB01_P HB01_N...
  • Page 47 TB-KU-xxx-ACDC8K Hardware User Manual For FMC 2 (J5): *1: GBTCLK[0:1]_M2C_P/N These clocks are connected to Quad 226 of the FPGA while this board provides an MMCX interface for one pair of clocks on Quad 227. The other pair is provided by the system clock buffer. *2: SCL, SDA The board provides test points with pull-up options to enable I2C communication with the FPGA.

  • Page 48: Fmc Hpc 3 (J8)

    TB-KU-xxx-ACDC8K Hardware User Manual 7.4.4. FMC HPC 3 (J8) This FMC connects GTH lanes and all of the available LA signals to banks on the FPGA. High Speed: Quad 126 and 127:  8 GTH lanes  2 differential clock pairs Low Speed: Bank 24: ...

  • Page 49: Table 7-8 Fmc 3 (J8) To Fpga Pinout

    TB-KU-xxx-ACDC8K Hardware User Manual Table 7-8 FMC 3 (J8) to FPGA Pinout Bank# Pin# Pin# Bank# CLK_DIR AF36 DP1_M2C_P AF37 DP1_M2C_N DP9_M2C_P DP9_M2C_N AE38 DP2_M2C_P AE39 DP2_M2C_N DP8_M2C_P DP8_M2C_N AC38 DP3_M2C_P AC39 DP3_M2C_N DP7_M2C_P AB36 DP7_M2C_N AB37 AA38 DP4_M2C_P AA39 DP4_M2C_N DP6_M2C_P DP6_M2C_N...
  • Page 50 TB-KU-xxx-ACDC8K Hardware User Manual FMC 3 (J8) Bank# Pin# Pin# Bank# *5 PG_C2M AH36 DP0_C2M_P AH37 DP0_C2M_N *1 GBTCLK0_M2C_P AD32 *1 GBTCLK0_M2C_N AD33 AG38 DP0_M2C_P AG39 DP0_M2C_N LA01_P_CC AL29 LA01_N_CC AM29 AP29 LA06_P AR30 LA06_N LA05_P AK32 LA05_N AL32 AM36 LA10_P LA09_P AU32...
  • Page 51 TB-KU-xxx-ACDC8K Hardware User Manual FMC 3 (J8) Bank# Pin# Pin# Bank# *5 PG_M2C HA01_P_CC HA01_N_CC HA00_P_CC HA00_N_CC HA05_P HA05_N HA04_P HA04_N HA09_P HA09_N HA08_P HA08_N HA13_P HA13_N HA12_P HA12_N HA16_P HA16_N HA15_P HA15_N HA20_P HA20_N HA19_P HA19_N HB03_P HB03_N HB02_P HB02_N HB05_P HB05_N...
  • Page 52 TB-KU-xxx-ACDC8K Hardware User Manual FMC 3 (J8) Bank# Pin# Pin# Bank# *7 VREF_A_M2C AL30 CLK1_M2C_P *5 PRSNT_M2C_L AM30 CLK1_M2C_N CLK0_M2C_P AM31 CLK0_M2C_N AN31 AM32 LA00_P_CC AN32 LA00_N_CC LA02_P AT29 LA02_N AT30 AV29 LA03_P AW29 LA03_N LA04_P AU29 LA04_N AU30 AW30 LA08_P AW31 LA08_N...
  • Page 53 TB-KU-xxx-ACDC8K Hardware User Manual FMC 3 (J8) Bank# Pin# Pin# Bank# *7 VREF_B_M2C CLK3_M2C_P CLK3_M2C_N CLK2_M2C_P CLK2_M2C_N HA03_P HA03_N HA02_P HA02_N HA07_P HA07_N HA06_P HA06_N HA11_P HA11_N HA10_P HA10_N HA14_P HA14_N HA17_P_CC HA17_N_CC HA18_P HA18_N HA21_P HA21_N HA22_P HA22_N HA23_P HA23_N HB01_P HB01_N...
  • Page 54 TB-KU-xxx-ACDC8K Hardware User Manual For FMC 3 (J8): *1: GBTCLK[0:1]_M2C_P/N These clocks are connected to Quad 126 of the FPGA while this board provides an MMCX interface for one pair of clocks on Quad 127. The other pair is provided by the system clock buffer. *2: SCL, SDA The board provides test points with pull-up options to enable I2C communication with the FPGA.

  • Page 55: Fmc Hpc 4 (J11)

    TB-KU-xxx-ACDC8K Hardware User Manual 7.4.5. FMC HPC 4 (J11) This FMC connects GTH lanes and 6 differential pairs of LA signals to banks on the FPGA. High Speed: Quad 228(XCKU060) / Quad 228 and 229(XCKU085):  4 GTH lanes (XCKU060) / 8 GTH lanes (XCKU085) ...

  • Page 56: Table 7-9 Fmc 4 (J11) To Fpga Pinout

    TB-KU-xxx-ACDC8K Hardware User Manual Table 7-9 FMC 4 (J11) to FPGA Pinout Bank# Pin# Pin# Bank# CLK_DIR 229(085) DP1_M2C_P 229(085) DP1_M2C_N DP9_M2C_P DP9_M2C_N 229(085) DP2_M2C_P 229(085) DP2_M2C_N DP8_M2C_P DP8_M2C_N 229(085) DP3_M2C_P 229(085) DP3_M2C_N DP7_M2C_P DP7_M2C_N DP4_M2C_P DP4_M2C_N DP6_M2C_P DP6_M2C_N DP5_M2C_P DP5_M2C_N *1 GBTCLK1_M2C_P *1 GBTCLK1_M2C_N...
  • Page 57 TB-KU-xxx-ACDC8K Hardware User Manual FMC 4 (J11) Bank# Pin# Pin# Bank# *5 PG_C2M 229(085) DP0_C2M_P 229(085) DP0_C2M_N *1 GBTCLK0_M2C_P *1 GBTCLK0_M2C_N 229(085) DP0_M2C_P 229(085) DP0_M2C_N LA01_P_CC LA01_N_CC LA06_P LA06_N LA05_P LA05_N LA10_P LA09_P LA10_N LA09_N LA13_P LA14_P LA13_N LA14_N LA17_P_CC LA17_N_CC LA18_P_CC LA18_N_CC...
  • Page 58 TB-KU-xxx-ACDC8K Hardware User Manual FMC 4 (J11) Bank# Pin# Pin# Bank# *5 PG_M2C HA01_P_CC HA01_N_CC HA00_P_CC HA00_N_CC HA05_P HA05_N HA04_P HA04_N HA09_P HA09_N HA08_P HA08_N HA13_P HA13_N HA12_P HA12_N HA16_P HA16_N HA15_P HA15_N HA20_P HA20_N HA19_P HA19_N HB03_P HB03_N HB02_P HB02_N HB05_P HB05_N...
  • Page 59 TB-KU-xxx-ACDC8K Hardware User Manual FMC 4 (J11) Bank# Pin# Pin# Bank# *7 VREF_A_M2C CLK1_M2C_P *5 PRSNT_M2C_L CLK1_M2C_N CLK0_M2C_P CLK0_M2C_N AG21 LA00_P_CC AG22 LA00_N_CC LA02_P LA02_N AE23 LA03_P AF23 LA03_N LA04_P LA04_N AD20 LA08_P AD21 LA08_N LA07_P LA07_N AE20 LA12_P AE21 LA12_N LA11_P LA11_N...
  • Page 60 TB-KU-xxx-ACDC8K Hardware User Manual FMC 4 (J11) Bank# Pin# Pin# Bank# *7 VREF_B_M2C CLK3_M2C_P CLK3_M2C_N CLK2_M2C_P CLK2_M2C_N HA03_P HA03_N HA02_P HA02_N HA07_P HA07_N HA06_P HA06_N HA11_P HA11_N HA10_P HA10_N HA14_P HA14_N HA17_P_CC HA17_N_CC HA18_P HA18_N HA21_P HA21_N HA22_P HA22_N HA23_P HA23_N HB01_P HB01_N...
  • Page 61 TB-KU-xxx-ACDC8K Hardware User Manual For FMC 4 (J11): *1: GBTCLK[0:1]_M2C_P/N These clocks are connected to Quad 228 (XCKU060 and 085) of the FPGA while this board provides an MMCX interface for one pair of clocks on Quad 229 (XCKU085). The other pair is provided by the system clock buffer.

  • Page 62: Fmc Hpc 5 (J14)

    TB-KU-xxx-ACDC8K Hardware User Manual 7.4.6. FMC HPC 5 (J14) This FMC connects GTH lanes (XCKU085 only) and 6 differential pairs of LA signals to banks on the FPGA. High Speed: No GTH (XCKU060) / Quad 230 and 231 (XCKU085):  8 GTH lanes (XCKU085) ...

  • Page 63: Table 7-10 Fmc 5 (J14) To Fpga Pinout

    TB-KU-xxx-ACDC8K Hardware User Manual Table 7-10 FMC 5 (J14) to FPGA Pinout Bank# Pin# Pin# Bank# CLK_DIR 231(085) DP1_M2C_P 231(085) DP1_M2C_N DP9_M2C_P DP9_M2C_N 231(085) DP2_M2C_P 231(085) DP2_M2C_N DP8_M2C_P DP8_M2C_N 231(085) DP3_M2C_P 231(085) DP3_M2C_N DP7_M2C_P 230(085) DP7_M2C_N 230(085) 230(085) DP4_M2C_P 230(085) DP4_M2C_N DP6_M2C_P 230(085)
  • Page 64 TB-KU-xxx-ACDC8K Hardware User Manual FMC 5 (J14) Bank# Pin# Pin# Bank# *5 PG_C2M 231(085) DP0_C2M_P 231(085) DP0_C2M_N *1 GBTCLK0_M2C_P 230(085) *1 GBTCLK0_M2C_N 230(085) 231(085) DP0_M2C_P 231(085) DP0_M2C_N LA01_P_CC LA01_N_CC LA06_P LA06_N LA05_P LA05_N LA10_P LA09_P LA10_N LA09_N LA13_P LA14_P LA13_N LA14_N LA17_P_CC LA17_N_CC...
  • Page 65 TB-KU-xxx-ACDC8K Hardware User Manual FMC 5 (J14) Bank# Pin# Pin# Bank# *5 PG_M2C HA01_P_CC HA01_N_CC HA00_P_CC HA00_N_CC HA05_P HA05_N HA04_P HA04_N HA09_P HA09_N HA08_P HA08_N HA13_P HA13_N HA12_P HA12_N HA16_P HA16_N HA15_P HA15_N HA20_P HA20_N HA19_P HA19_N HB03_P HB03_N HB02_P HB02_N HB05_P HB05_N...
  • Page 66 TB-KU-xxx-ACDC8K Hardware User Manual FMC 5 (J14) Bank# Pin# Pin# Bank# *7 VREF_A_M2C CLK1_M2C_P *5 PRSNT_M2C_L CLK1_M2C_N CLK0_M2C_P CLK0_M2C_N AD25 LA00_P_CC AE25 LA00_N_CC LA02_P LA02_N AG26 LA03_P AG27 LA03_N LA04_P LA04_N AE27 LA08_P AF27 LA08_N LA07_P LA07_N AD26 LA12_P AE26 LA12_N LA11_P LA11_N...
  • Page 67 TB-KU-xxx-ACDC8K Hardware User Manual FMC 5 (J14) Bank# Pin# Pin# Bank# *7 VREF_B_M2C CLK3_M2C_P CLK3_M2C_N CLK2_M2C_P CLK2_M2C_N HA03_P HA03_N HA02_P HA02_N HA07_P HA07_N HA06_P HA06_N HA11_P HA11_N HA10_P HA10_N HA14_P HA14_N HA17_P_CC HA17_N_CC HA18_P HA18_N HA21_P HA21_N HA22_P HA22_N HA23_P HA23_N HB01_P HB01_N...
  • Page 68 TB-KU-xxx-ACDC8K Hardware User Manual For FMC 5 (J14): *1: GBTCLK[0:1]_M2C_P/N These clocks are connected to Quad 230 (XCKU085 only) of the FPGA while this board provides an MMCX interface for one pair of clocks on Quad 231 (XCKU085 only). The other pair is provided by the system clock buffer.

  • Page 69: Fmc Hpc 6 (J19)

    TB-KU-xxx-ACDC8K Hardware User Manual 7.4.7. FMC HPC 6 (J19) This FMC connects GTH lanes and 6 differential pairs of LA signals to banks on the FPGA. High Speed: Quad 128:  4 GTH lanes  2 differential clock pairs Low Speed: Bank 24: ...

  • Page 70: Table 7-11 Fmc 6 (J19) To Fpga Pinout

    TB-KU-xxx-ACDC8K Hardware User Manual Table 7-11 FMC 6 (J19) to FPGA Pinout Bank# Pin# Pin# Bank# CLK_DIR DP1_M2C_P DP1_M2C_N DP9_M2C_P DP9_M2C_N DP2_M2C_P DP2_M2C_N DP8_M2C_P DP8_M2C_N DP3_M2C_P DP3_M2C_N DP7_M2C_P DP7_M2C_N DP4_M2C_P DP4_M2C_N DP6_M2C_P DP6_M2C_N DP5_M2C_P DP5_M2C_N *1 GBTCLK1_M2C_P *1 GBTCLK1_M2C_N DP1_C2M_P DP1_C2M_N DP9_C2M_P DP9_C2M_N...
  • Page 71 TB-KU-xxx-ACDC8K Hardware User Manual FMC 6 (J19) Bank# Pin# Pin# Bank# *5 PG_C2M DP0_C2M_P DP0_C2M_N *1 GBTCLK0_M2C_P *1 GBTCLK0_M2C_N DP0_M2C_P DP0_M2C_N LA01_P_CC LA01_N_CC LA06_P LA06_N LA05_P LA05_N LA10_P LA09_P LA10_N LA09_N LA13_P LA14_P LA13_N LA14_N LA17_P_CC LA17_N_CC LA18_P_CC LA18_N_CC LA23_P LA23_N LA27_P LA26_P...
  • Page 72 TB-KU-xxx-ACDC8K Hardware User Manual FMC 6 (J19) Bank# Pin# Pin# Bank# *5 PG_M2C HA01_P_CC HA01_N_CC HA00_P_CC HA00_N_CC HA05_P HA05_N HA04_P HA04_N HA09_P HA09_N HA08_P HA08_N HA13_P HA13_N HA12_P HA12_N HA16_P HA16_N HA15_P HA15_N HA20_P HA20_N HA19_P HA19_N HB03_P HB03_N HB02_P HB02_N HB05_P HB05_N...
  • Page 73 TB-KU-xxx-ACDC8K Hardware User Manual FMC 6 (J19) Bank# Pin# Pin# Bank# *7 VREF_A_M2C CLK1_M2C_P *5 PRSNT_M2C_L CLK1_M2C_N CLK0_M2C_P CLK0_M2C_N AH29 LA00_P_CC AJ29 LA00_N_CC LA02_P LA02_N AH31 LA03_P AH32 LA03_N LA04_P LA04_N AH28 LA08_P AJ28 LA08_N LA07_P LA07_N AE30 LA12_P AF30 LA12_N LA11_P LA11_N...
  • Page 74 TB-KU-xxx-ACDC8K Hardware User Manual FMC 6 (J19) Bank# Pin# Pin# Bank# *7 VREF_B_M2C CLK3_M2C_P CLK3_M2C_N CLK2_M2C_P CLK2_M2C_N HA03_P HA03_N HA02_P HA02_N HA07_P HA07_N HA06_P HA06_N HA11_P HA11_N HA10_P HA10_N HA14_P HA14_N HA17_P_CC HA17_N_CC HA18_P HA18_N HA21_P HA21_N HA22_P HA22_N HA23_P HA23_N HB01_P HB01_N...
  • Page 75 TB-KU-xxx-ACDC8K Hardware User Manual For FMC 6 (J19): *1: GBTCLK[0:1]_M2C_P/N These clocks are connected to Quad 128 of the FPGA while this board provides an MMCX interface for one pair of clocks on Quad 232 (XCKU085 only). The other pair is provided by the system clock buffer. *2: SCL, SDA The board provides test points with pull-up options to enable I2C communication with the FPGA.

  • Page 76: Ddr4 Sdram

    TB-KU-xxx-ACDC8K Hardware User Manual 7.5. DDR4 SDRAM This TB-KU-xxx-ACDC8K development board includes 8 DDR4 SDRAM memory components (Micron EDY4016AABG-DR-F). Control and address signals are wired in a fly-by routing topology. DDR4 SDRAM Capacity: 4Gbit (32M words x 16 bits x 8) x 8 components Address Bus: 15bit (Row Address: 15bit, Column Address: 10bit) Bank Address: 2bit Bank Group: 1bit...

  • Page 77: Sfp+ Connectors

    TB-KU-xxx-ACDC8K Hardware User Manual 7.6. SFP+ Connectors Located on the front panel of the TB-KU-xxx-ACDC8K are 4 SFP+ slots available to the user. These ports are standard single SFP+ modules. For each of these modules, a 3-pin connector is available to jumper between either RX_LOS or TX_FAULT.

  • Page 78: Table 7-12 Sfp+ I2C Bus Pin Assignment

    TB-KU-xxx-ACDC8K Hardware User Manual The SFP+ I2C multiplexed data and multiplexed clocks are connected to the FPGA’s Bank 64. Table 7-12 SFP+ I2C Bus Pin Assignment Signal Name FPGA Bank CLK_SFP_I2C_FPGA_OD AF19 SDA_SFP_I2C_FPGA_OD AG19 Also, pins RS0 and RS1 have been connected together to efficiently make use of available connections. By connecting these together the optical transmit and receive signals operate at the same rate.

  • Page 79: Usb To Uart Controller

    Both the UART transmit and receive data signals are connected as well as flow control signals. Using the PC’s virtual COM port drivers, there are different supported baud rates that are compatible with this controller and can be set during the COM port configuration. TB-KU-060/075-ACDC8K Terminal 1.8V...

  • Page 80: Battery

    TB-KU-xxx-ACDC8K Hardware User Manual 7.8. Battery This board contains an 11.6 mm coin cell battery connected to the VBATT pin which serves as a battery backup supply for the FPGA’s internal volatile memory that stores the key for AES decryption. More information is available in Xilinx’s UltraScale configuration UG570 document.

  • Page 81: Dual Quad (X8) Spi Flash

    TB-KU-xxx-ACDC8K Hardware User Manual 7.9. Dual Quad (x8) SPI Flash This board has a 256Mbit dual quad SPI flash (x8) memory for FPGA configuration purposes. Please refer to Xilinx’s UltraScale configuration UG570 document on Master SPI Dual Quad (x8) for more information.

  • Page 82: Jtag And Pmod Interface

    TB-KU-xxx-ACDC8K Hardware User Manual Table 7-16 SPI Flash Memory Pin Assignment FPGA Signal Name FPGA Bank Primary Flash SPIFLASH_HR_1_CS_N SPIFLASH_HR_1_IO_0 AE11 SPIFLASH_HR_1_IO_1 AD10 SPIFLASH_HR_1_IO_2 SPIFLASH_HR_1_IO_3 CLK_FPGA_CCLK AC11 Secondary Flash SPIFLASH_HR_2_CS_N AW16 SPIFLASH_HR_2_IO_0 AF14 SPIFLASH_HR_2_IO_1 AG14 SPIFLASH_HR_2_IO_2 AE13 SPIFLASH_HR_2_IO_3 AF13 CLK_FPGA_CCLK AC11 Xilinx Core User IO SPIFLASH_ZYNQ_CS_N...

  • Page 83: Pmod Interface

    TB-KU-xxx-ACDC8K Hardware User Manual 7.10.2. Pmod Interface Digilent’s Pmod standard for system boards that provide I2C connectors is to use a male header. This board features a 0.1” straight 2x6 male header for Pmod connections which includes 3.3V and ground signals and eight I/O.

  • Page 84: General Purpose Leds

    TB-KU-xxx-ACDC8K Hardware User Manual 7.11. General Purpose LEDs The TB-KU-xxx-ACDC8K has 16 user programmable LEDs. There are 8 green colored LEDs and 8 red ones. The FPGA can be programmed to output a logic “high” to turn on a LED and a logic “low” to turn it off.

  • Page 85: General Purpose Switches

    TB-KU-xxx-ACDC8K Hardware User Manual 7.12. General Purpose Switches 7.12.1. DIP Switches This board is equipped of 4 Copal Electronics CHS-04TA SPST 4-positions DIP switches. Slide in the ON position for a logic “high”. Table 7-21 DIP Switches Pin Assignment Switch RefDes Signal Name FPGA Bank FPGA Pin...

  • Page 86: Jumper Switches

    TB-KU-xxx-ACDC8K Hardware User Manual 7.12.3. Jumper Switches Lastly, 8 jumper switches were conveniently placed at the user’s disposal available as a standard 16-pin header. It provides uncommitted GPOs that connect to the board’s FPGA. Figure 7-18 Jumper Switches Structure The signals output logic “high” by default (when there is no jumper connected). Connect an odd-numbered pin to the even-numbered pin across from it to output a logic “low”...

  • Page 87: Appendix

    TB-KU-xxx-ACDC8K Hardware User Manual 8. Appendix 8.1. Default Settings Following Figure shows a setting Jumper and DIP switches. SW17,18,19.20 Figure 8-1 Jumper and Switch location (Component Side) Table 8-1 Default Settings Silk No. Initial Setting Function POR Override (ON/OFF) ALL OFF Video Clock setting SW17,18,19,20 ALL OFF...

  • Page 88: Power Sequencer Timings

    TB-KU-xxx-ACDC8K Hardware User Manual 8.2. Power Sequencer Timings Figure 8-2 Power Sequencer Default Settings Rev. 1.03...
  • Page 89 TB-KU-xxx-ACDC8K Hardware User Manual Inrevium Company URL: http://solutions.inrevium.com/ http://solutions.inrevium.com/jp/ E-mail: psd-support@teldevice.co.jp HEAD Quarter: Yokohama East Square, 1-4 Kinko-cho, Kanagawa-ku, Yokohama City, Kanagawa, Japan 221-0056 TEL: +81-45-443-4031 FAX: +81-45-443-4063 Rev. 1.03...

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