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TB-FMCH-HDMI2 Hardware User Manual Introduction Thank you for purchasing the TB-FMCH-HDMI2-RX/TB-FMCH-HDMI2-TX boards. Before using the product, be sure to carefully read this user manual and fully understand how to correctly use the product. First read through this manual, then always keep it handy.
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TB-FMCH-HDMI2 Hardware User Manual Warning In the event of a failure, disconnect the power supply. If the product is used as is, a fire or electric shock may occur. Disconnect the power supply immediately and contact our sales personnel for repair.
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TB-FMCH-HDMI2 Hardware User Manual Caution Do not use or place the product in the following locations. Humid and dusty locations Airless locations such as closet or bookshelf Locations which receive oily smoke or steam Locations exposed to direct sunlight ...
Accessories: Interboard spacers and screws Interboard jumper cable 2. Overview The TB-FMCH-HDMI2 comes either with AnalogDevices’s HDMI Receiver "ADV7612BSWZ-P" or HDMI Transmitter "ADV7511KSTZ-P". (Collectively, there are called TB-FMCH-HDMI2. This document specifically describes these optional boards in the RX and TX sections respectively).
TB-FMCH-HDMI2 Hardware User Manual 3. Feature HDMI Devices Receiver : AnalogDevices’s ADV7612BSWZ-P Transmitter : AnalogDevices’s ADV7511KSTZ-P FMC Connector : Samtec’s ASP-134488-01 HDMI Connector (common) : Molex’s 5002541927 Power Supply (common) : Jumper switch selection The RX board has an EEPROM for Display Data Channel (hereafter referred to as DDC) and allows setting the AnalogDevices’s ADV7612BSWZ-P board operation via jumpers.
TB-FMCH-HDMI2 Hardware User Manual 4. TB-FMCH-HDMI2-RX 4.1. Block Diagram Figure 4-1 shows the TB-FMCH-HDMI2-RX block diagram. The FMC-HPC connector is mounted on the solder side of the board. FMC-HPC FPGA DEC#0 HDMI#0(RX) RX#0_P[35:0] RX#0_C、RX#0_0~2 RX#0_VS/HS/DE RX#0_DDCA_SCL LA[33:00]_P/N RX#0_LLC RX#0_DDCA_SDA HA[23:00]_P/N...
TB-FMCH-HDMI2 Hardware User Manual 4.2. External View of the Board Figures 4-2 and 4-3 show the external view of the TB-FMCH-HDMI2-RX board. Caution : This board has a plastic cover for protecting HDMI devices. Do not remove a plastic cover. FPGA...
TB-FMCH-HDMI2 Hardware User Manual 4.5. HDMI Receiver HDMI Connector uses a 5002541927 (MOLEX). HDMI Receiver uses an ADV7612BSWZ-P (Analog Devices). The following device is used as ESD protection. ESD protection: RCLAMP0524 and RCLAMP0504 (Semtech) Table 4-1 shows the HDMI connector pin assignments.
FMC Connector The FMC connector (High-Pin Count) connecting to the main board uses an ASP-134488-01 (SAMTEC). Power to the TB-FMCH-HDMI2-RX is supplied from a +12V on the main board. An external power source can also be used. Table 4-3 shows JP1 jumper setting for power supply.
TB-FMCH-HDMI2 Hardware User Manual 4.7. Other Interfaces The board also has the following interfaces. 4.7.1. EEPROM Interface I2C interface used to control the EEPROM from the FPGA EEPROM device: 24LCS22A-SN (Micro Chip) 4.7.2. JTAG Interface JTAG connector for FPGA configuration...
TB-FMCH-HDMI2 Hardware User Manual 4.8. LED Status Table 4-6 shows the onboard LEDs. Table 4-6 LED Status Circuit # Silk Purpose Description LED0 General-purpose LED0 [RX0]I2C config state Off: CFG done / On: CFG active LED1 General-purposeLED1 [RX0]I2C read back...
TB-FMCH-HDMI2 Hardware User Manual 4.10. FPGA Pin Assignment Table 4-8 shows the FPGA pin assignment. In case of 8-bit signal format, active bits are assigned to MSB 8-bit of each RGB pin of FMC. LSB 2-bit are always 2'b00 in 8-bit signal format.
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TB-FMCH-HDMI2 Hardware User Manual Pin Name Spec Description LA00_N_CC LVCMOS25 RX#1_VSYNC signal (FPGA to FMC) LA01_N_CC LVCMOS25 RX#1_HSYNC signal (FPGA to FMC) LA02_N LVCMOS25 RX#1_DE signal (FPGA to FMC) LA03_N LVCMOS25 RX#1_P0 signal (FPGA to FMC) [B0] LA04_N LVCMOS25 RX#1_P1 signal (FPGA to FMC)
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TB-FMCH-HDMI2 Hardware User Manual Pin Name Spec Description HA22_N LVCMOS25 Unused HA23_N LVCMOS25 Unused RX#0_P35 LVCMOS33 RX#0 Video data 35 (RX to FPGA) RX#0_P34 LVCMOS33 RX#0 Video data 34 (RX to FPGA) RX#0_P33 LVCMOS33 RX#0 Video data 33 (RX to FPGA)
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TB-FMCH-HDMI2 Hardware User Manual Pin Name Spec Description SYSCLK_P LVCMOS33 System Clock (27MHz) RX#0_HSYNC LVCMOS33 RX#0 HSYNC (RX to FPGA) RX#0_VSYNC LVCMOS33 RX#0 VSYNC (RX to FPGA) RX#0_SPDIF AA10 LVCMOS33 RX#0 SPDIF Digital Audio (RX to FPGA) RX#0_I2S0 AB10 LVCMOS33...
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TB-FMCH-HDMI2 Hardware User Manual Pin Name Spec Description RX#1_P13 LVCMOS33 RX#1 Video Data 13 (RX to FPGA) RX#1_P12 LVCMOS33 RX#1 Video Data 12 (RX to FPGA) RX#1_P11 LVCMOS33 RX#1 Video Data 11 (RX to FPGA) RX#1_P10 LVCMOS33 RX#1 Video Data 10 (RX to FPGA)
TB-FMCH-HDMI2 Hardware User Manual 4.11. FPGA Output Data Phase Figure 4-6 shows the output data phase of FPGA on TB-FMCH-HDMI2-RX. FPGA to FMC data is output at the falling edge of the video clock. The data should be latched at the rising edge on the main board side.
TB-FMCH-HDMI2 Hardware User Manual 5. TB-FMCH-HDMI2-TX 5.1. Block Diagram Figure 5-1 shows a TB-FMCH-HDMI2-TX block diagram. The FMC-HPC connector is mounted on the solder side of the board. FMC-HPC FPGA ENC#0 HDMI#0(TX) TX#0_D[35:0] TX#0_C、TX#0_0~2 TX#0_VS/HS/DE TX#0_DDCA_SCL LA[33:00]_P/N TX#0_CLK TX#0_DDCA_SDA HA[23:00]_P/N...
TB-FMCH-HDMI2 Hardware User Manual 5.2. External View of the Board Figures 5-2 and 5-3 show the external view of the TB-FMCH-HDMI2-TX board. FPGA HDMI Transmitter HDMI Connector Figure 5-2 TB-FMCH-HDMI2-TX (component side) FMC-HPC Figure 5-3 TB-FMCH-HDMI2-TX (solder side) Rev.1.05...
TB-FMCH-HDMI2 Hardware User Manual 5.5. HDMI Transmitter The HDMI connector uses MOLEX’s 5002541927. The HDMI transmitter uses Analog Devices’s ADV7511KSTZ-P. The following device is used for ESD protection: ESD protection: Semtech’s RCLAMP0524 and RCLAMP0504 Table 5-1 shows the HDMI connector pin assignment.
FMC Connector The FMC connector connecting to the High-Pin Count uses SAMTEC’s ASP-134488-01. Power to the TB-FMCH-HDMI2-TX is supplied from a +12V on the main board. An external power source can also be used. Table 5-2 shows JP3 jumper setting for power supply.
TB-FMCH-HDMI2 Hardware User Manual 5.7. Other Interfaces The board also provides the following interfaces. 5.7.1. JTAG Interface The board has a JTAG connector FPGA configuration. JTAG Connector: Molex’s 87832-1420 Table 5-4 JTAG Connector Signal Signal Name 3.3V 5.7.2. General-Purpose Clock Interface The board has a general-purpose clock on FPGA (27MHz crystal oscillator) KC5032C027.0000C30E00 (Kyocera)
12V display On: 12V active 5.9. Relation of ROM and Input Video Format TB-FMCH-HDMI2-RX and TB-FMCH-HDMI2-TX have 3 types of FPGA ROM. Relation between ROM and Input Format is below. Table 5-6 Relation of ROM and Input Video Format HDMI...
TB-FMCH-HDMI2 Hardware User Manual 5.10. Control Function Table 5-7 shows the onboard switch function. Table 5-7 Switch Function Circuit # Silk Description S1-1 ADV7511 config ROM selection: 8bit Output : S1-1 OFF, S1-2 ON, S1-3 ON, S1-4 ON S1-2 10bit Output : S1-1 ON, S1-2 ON, S1-3 OFF, S1-4 ON...
TB-FMCH-HDMI2 Hardware User Manual 5.11. FPGA Pin Assignment Table 5-8 shows the FPGA pin assignment. In case of 8-bit signal format, active bits are assigned to MSB 8-bit of each RGB pin of FMC. LSB 2-bit are always 2'b00 in 8-bit signal format.
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TB-FMCH-HDMI2 Hardware User Manual Pin Name Spec. Description LA00_N_CC LVCMOS25 TX#1_VSYNC Signal (FMC to FPGA) LA01_N_CC LVCMOS25 TX#1_HSYNC Signal (FMC to FPGA) LA02_N LVCMOS25 TX#1_DE Signal (FMC to FPGA) LA03_N LVCMOS25 TX#1_D0 Signal (FMC to FPGA) [B0] LA04_N LVCMOS25 TX#1_D1 Signal (FMC to FPGA)
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TB-FMCH-HDMI2 Hardware User Manual Pin Name Spec. Description HA22_N LVCMOS25 Unused HA23_N LVCMOS25 Unused TX#0_D35 LVCMOS33 TX#0 Video data 35 (FPGA to TX) TX#0_D34 LVCMOS33 TX#0 Video data 34 (FPGA to TX) TX#0_D33 LVCMOS33 TX#0 Video data 33 (FPGA to TX)
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TB-FMCH-HDMI2 Hardware User Manual Pin Name Spec. Description TX#0_VSYNC LVCMOS33 TX#0 VSYNC (FPGA to TX) TX#0_DSD0 LVCMOS33 TX#0 DSD Audio data 0 (FPGA to TX) TX#0_DSD1 LVCMOS33 TX#0 DSD Audio data 1 (FPGA to TX) TX#0_DSD2 LVCMOS33 TX#0 DSD Audio data 2 (FPGA to TX)
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TB-FMCH-HDMI2 Hardware User Manual Pin Name Spec. Description TX#1_D15 LVCMOS33 TX#1 Video data 15 (FPGA to TX) TX#1_D14 LVCMOS33 TX#1 Video data 14 (FPGA to TX) TX#1_D13 LVCMOS33 TX#1 Video data 13 (FPGA to TX) TX#1_D12 LVCMOS33 TX#1 Video data 12 (FPGA to TX)
TB-FMCH-HDMI2 Hardware User Manual 5.12. FPGA Input Data Phase Figure 5-6 shows the input data phase of the FPGA on the TB-FMCH-HDMI2-TX. FMC connector to FPGA data is captured by the FPGA at the rising edge of a video clock. Data from the main board is transferred at the falling edge of a video clock.
TB-FMCH-HDMI2 Hardware User Manual Table 7-2 TB-FMCH-HDMI2-RX Default Setting (DSW/RSW) Silk No. Default Setting S1-1 S1-2 S1-3 S1-4 S1-5 S1-6 S1-7 S1-8 For the setting at the time of use, refer to Table 4-7 Switches Rev.1.05...
TB-FMCH-HDMI2 Hardware User Manual Table 7-4 TB-FMCH-HDMI2-TX Default Switch Settings (DSW/RSW) Silk No. Default Setting S1-1 S1-2 S1-3 S1-4 S1-5 S1-6 S1-7 S1-8 For the setting at the time of use, refer to Table 5-7 Switch Function. Rev.1.05...
8. Usage Example Figure 8-1 shows a usage example. Be careful about the jumper setting of the TB-6S-LX150T-IMG2 main board. If the image is not output, push the S3 of the TB-FMCH-HDMI2-RX or TB-FMCH-HDMI2-TX for only a short period of time. TB-FMCH-HDMI2-RX...
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TB-FMCH-HDMI2 Hardware User Manual Rev.1.05...
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TB-FMCH-HDMI2 Hardware User Manual PLD Solution Dept. PLD Division URL: http://solutions.inrevium.com/ E-mail: psd-support@teldevice.co.jp HEAD Quarter: Yokohama East Square, 1-4 Kinko-cho, Kanagawa-ku, Yokohama City, Kanagawa, Japan 221-0056 TEL: +81-45-443-4016 FAX: +81-45-443-4058 Rev.1.05...