Figure 3-17. Timerex Register - Brainboxes AD-593 User Manual

Register Map
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Figure 3-17. TIMEREX Register.

TIMEREX Timer Counter Extended Mode Register.
BIT 7
021F XMODE
Hex 7
R/W
Bits 0-5, TIMER Pacer Clock Divisor Bits. ____________________________________ _
The lower 6 bits of the TIMEREX register, TIMER 0-5,
are used to select the pacer clock frequency. The bit pattern
written selects the divisor factor applied to the fundamental
frequency, as given in the following table. The source of the
fundamental clock frequency is either the on board 600kHz
oscillator or a user supplied external clock and is chosen by the
MODE 0 & 1 bits in the ADCSR register.
When strobing the A/D converter do not choose pacer clock
frequencies above the maximum throughput of the converter.
eg 30kHz
eg 100kHz
Do not exceed the throughputs of the D/A converters, DAC0 and
DAC1, or the Digital i/o port when using pacer clock strobes in
the AD1200 cards Extended Modes.
eg 100kHz
eg 1MHz
Chapter 3
BIT 6 BIT 5
XMODE TIMER
6 5
R/W R/W
for AD1211 and AD1221
for AD1200/01, AD1210 and AD1210
for AD1200 D/A converters DAC0 or DAC1
for AD1200 Digital Input or Output ports
BIT 4 BIT 3
TIMER TIMER
4 3
R/W R/W
AD1200 Reference
BIT 2 BIT 1
TIMER TIMER
2 1
R/W R/W
__________ _ Read/Write.
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BIT 0
TIMER
0
R/W