Dma, Direct Memory Access; The Pacer Clock - Brainboxes AD-593 User Manual

Introduction
The users software, built from the Real World driver, thus
sets up the interrupt hardware, starts the first conversion. The
separate ISR services each conversion whenever it happens and
finally disables the conversion. In between conversions the PC
and the program are free to perform other tasks, eg updating a
graph on the screen.
Thus interrupt driven i/o is used for medium sample rate
continuous conversions or when continuous conversions across
over several inputs channels and gain combinations are required.
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DMA, Direct Memory Access.

In DMA, direct memory access, mode, the DMA controller
is programmed with the number of conversions to be taken,
DMA is enabled and the start of the first conversion is triggered.
When the conversion is done, the A/D Done bit is set and this
automatically commences a DMA input cycle. The DMA
controller reads the ADCLO and then the ADCHI input registers
placing the data straight into memory without the help of the
computers micro processor. When the last of the conversions
takes place, the DMA controller sets the TC line true when
reading the ADCHI byte thus disabling further A/D conversions
and, if necessary, stopping the pacer clock.
The users software, built from the Real World driver, thus
merely sets up the DMA hardware and starts the first
conversion. From then on till the last conversion takes place the
PC and the program are completely free to perform other tasks,
eg updating a graph on the screen.
Thus DMA driven i/o is used for the maximum rate
continuous conversions but only with a single channel/gain
combination.
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The Pacer Clock.

The pacer clock can be used to trigger the A/D converter
thus forcing the start of conversion to be at precisely timed
intervals. When the clock is enabled the users program is not
only relieved of the burden of determining WHEN to start the
Chapter 1
AD1200 Reference
Page 13