Register Map
___________________
Power Up Conditions.
On power up all registers are set to zero.
____________________________ _
The A/D Control Status Register.
The most important register in the AD1200 series of cards
is the control status register. It is the primary control register for
the AD Converter, it holds the A/D Busy and A/D Done bits
which indicate whether an A/D conversion is in progress or
finished, its A/D Error and Clear Error bits are used to detect
and service A/D overrun or triggering mistakes. The DMA and
Interrupt enable bits are used to decide whether the A/D Done
bit causes a DMA read or system interrupt. Finally its Mode bits
determine whether single shot or continuous A/D conversions are
performed and what initiates the repetitive conversions and at
what rate they occur.
__________________________________ _
Figure 3-2. A/D Control Status Register.
ADCSR A/D Control Status Register.
BIT 7
0218 A/D
Hex DONE
Read
Bit 7 A/D Done, Read Only.
________________________
This bit is indicates that the A/D converter has a reading
ready.
Set By:
The A/D converter when it has finished converting an
analogue input.
If Bit 3, DMA Enable, of the ADCSR is also set
then a DMA cycle will be generated when this bit is
set by the ADC.
If Bit 2, Interrupt Enable, of the ADCSR is also set,
but not Bit 3, then an interrupt will be generated
when this bit is set by the ADC.
Chapter 3
BIT 6
BIT 5
A/D
A/D
ERROR
BUSY
Read
Read
BIT 4
BIT 3
CLEAR
DMA
ERROR
ENABLE ENABLE BIT 1
Write
R/W
AD1200 Reference
BIT 2
BIT 1
INT
MODE
R/W
R/W
Page 53
BIT 0
MODE
BIT 0
R/W