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Introduction
the pacer clock at the chosen rate, based on the 600kHz
oscillator or external clock input as selected by the
ADCSR Mode bits.
The pacer clock strobes the converters at precisely timed
intervals. The pacer clock also causes an interrupt or DMA
cycle which then updates the DACLO and DACHI
registers ready for the next pacer clock strobe.
vi)
When the required number of conversion has taken place
the pacer clock is stopped either by the interrupt service
routine or by the DMA TC, terminal count signal.
The clock may also stopped by a write to the ADCSR.
_______________
Digital I/O Ports.
The digital input port is an 8 bit LS TTL compatible port,
it is a read only port.
The digital output port is an 8 bit LS TTL compatible port,
it is a write only port.
Digital Port Programmed I/O.
__________________________
Digital i/o is usually performed using programmed i/o. As
the data is written to the digital output register the bit pattern
immediately appears on the digital output pins. A read of the
digital input register latches the current bit pattern present on the
digital input pins returning it as an 8 bit data byte.
Digital Port Interrupts and DMA.
_____________________________ _
The AD1200 card only has the ability to use the digital
input and output port in interrupt driven or DMA modes. The
mode bits in the ADCSR in conjunction with bits 6 & 7 in the
TIMER register are used to specify the digital port, instead of
the A/D converter, as the target for the pacer clock strobes.
i)
The mode bits in the ADCSR, A/D Control Status
Register, register 0, should be set to 01, 02 or 03, ie Mode
1, 2 or 3.
This stops the pacer clock if it is running.
ii)
The XMODE bits in the TIMER register is set to C0 hex
Chapter 1
AD1200 Reference
_________________ _
AD1200 Card Only.
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