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TK-7108
■ Squelch Circuit
The detection output from the FM IF IC (IC5) passes
through a noise amplifier (Q18) to detect noise. A voltage is
applied to the CPU (IC6). The CPU controls squelch accord-
ing to the voltage (SQIN) level. The signal from the RSSI pin
of IC5 is monitored. The electric field strength of the re-
ceive signal can be known before the SQIN voltage is input
to the CPU, and the scan stop speed is improved.
PLL Frequency Synthesizer
The PLL circuit generates the first local oscillator signal
for reception and the RF signal for transmission.
■ PLL
The frequency step of the PLL circuit is 5 or 6.25kHz. A
16.8MHz reference oscillator signal is divided at IC1 by a
fixed counter to produce the 5 or 6.25kHz reference fre-
quency. The voltage controlled oscillator (VCO) output sig-
nal is buffer amplified by Q15, then divided in IC1 by a dual-
module programmable counter. The divided signal is com-
pared in phase with the 5 or 6.25kHz reference signal in the
phase comparator in IC1. The output signal from the phase
comparator is filtered through a low-pass filter and passed
to the VCO to control the oscillator frequency. (See Fig. 6)
■ VCO
The operating frequency is generated by Q11 in transmit
mode and Q10 in receive mode. The oscillator frequency is
controlled by applying the VCO control voltage, obtained
from the phase comparator, to the varactor diodes (D10 and
D12 in transmit mode and D9 and D11 in receive mode).
The TX/RX pin is set low in receive mode causing Q12 and
Q7 to turn Q11 off, and turn Q10 on. The TX/RX pin is set
high in transmit mode. The outputs from Q10 and Q11 are
amplified by Q15 and sent to the RF amplifiers.
IC1 : PLL IC
PLL
DATA
16.8MHz
18
CIRCUIT DESCRIPTION / 电路说明
IC5
AF
IF
SYSTEM
RSSI
Fig. 5 Squelch circuit / 图5 静噪电路
5kHz/6.25kHz
1/N
Phase
Charge
comparator
pump
REF
OSC
1/M
5kHz/6.25kHz
Fig. 6 PLL circuit / 图6 锁相环电路
■ 静噪电路
从调频中频芯片(IC5)输出的检测经过噪音放大器 (Q18)检测
噪音。向CPU (IC6)输入电压。CPU按照电压(SQIN)电平控制静
噪。来自于IC5的RSSI管脚的信号被监听。在SQIN电压被输入
到CPU之前可以识别接收信号的电场强度，并且扫描停止速度
将增快。
Q18
NOISE AMP
D18
IC6
SQIN
DET
CPU
RSSI
锁相环频率合成器
锁相环电路产生接收机的第一本振信号和用于发射的射频载
波信号。
■ 锁相环电路
锁相环电路的步进频率为 5 或 6.25kHz。 16.8MHz 的参考振荡
器信号通过一个混合计数器在芯片 I C 1 中被分频生成 5 或
6.25kHz 参考频率。压控振荡器（VCO）输出信号通过 Q15 被缓
冲放大，然后在芯片 IC1 中被双模可编程计数器分频。被分频
的信号在带有 5 或 6.25kHz 参考信号的相位比较器的芯片 IC1 中
被比较。从相位比较器输出的信号进入一个低通滤波器后，通
过压控振荡器控制振荡频率。 （参见图 6）
■ 压控振荡器
在发射模式中通过Q11产生操作频率，在接收模式中通过
Q10产生操作频率。控制信号通过相位比较器到变容二极管 (在
发射中为D10和 D12，在接收模式中为 D9和D11)。 在接收模式
中，由于Q12和Q7切断Q11并且导通 Q10 ，所以发射／接收管
脚设置为低电平。发射-接收管脚在发射模制内被设置为高电
频。来自于Q10 和Q11的输出被 Q15放大并送至RF放大器。
Q11
TX VCO
LPF
D10,12
Q10
RX VCO
D9,11
Q3
AMP
Q15
BUFF
AMP
Q7,12
T/R SW
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