Kenwood TK-5210 Service Manual page 19

TK-5210
5. PLL Frequency Synthesizer
The PLL Frequency Synthesizer consists of the following
components:
• VCXO (X301)
• VCO (Q310, Q311)
• Rheostat (IC414)
• PLL IC (IC303)
• 1/2 divider (IC304)
• Local switch (D101, D210)
5-1. VCXO (X301)
VCXO (X301) generates a reference frequency of 16.8
MHz for the PLL frequency synthesizer. This reference
frequency is applied to pin 8 of the PLL IC (IC303).
The VCXO oscillation frequency is fine-adjusted by
controlling the voltage applied to pin 1 of the VCXO with DAC
(IC411). It is also controlled with pin 1 of the VCXO if the
output from VCXO is modulated.
5-2. VCO
There is a RX VCO and a TX VCO.
The TX VCO (Q311) generates a transmit carrier and the
RX VCO (Q310) generates a 1st local receive signal.
For the VCO oscillation frequency, the transmit carrier is
272 to 348 MHz and the 1st local receive signal is 371.9 to
447.9 MHz.
The VCO oscillation frequency is determined by one
system of operation switching terminal "T/R" and two
systems of voltage control terminals "C/V" and "V-assist".
The operation switching terminal, "T/R", is controlled by
the control line (T/R) output from the CPU (IC5). When the T/
R logic is low, the VCO outputs the transmit carrier and when
it is high, it outputs a 1st local receive signal.
The voltage control terminals, "CV" and "V-assist", are
controlled by the PLL IC (IC303) and rheostat (IC414) and the
output frequency changes continuously according to the
applied voltage. For the modulation input terminal, "MOD",
the output frequency changes according to the applied
voltage. This is used to modulate the VCO output. "MOD"
works only when "T/R" is low.
5-3. Rheostat (IC414)
The rheostat (IC414) is connected to the VCO voltage
control terminal, "V-assist", and quickly controls the VCO
oscillation frequency. However, its accuracy is low and the
VCO frequency cannot be matched accurately with the
desired transmit carrier or the 1st local receive signal.
The rheostat is controlled by the CPU (IC5) through the 3-
line "PCS", "DAT", "CLK" serial bus.
5-4. PLL IC (IC303)
PLL IC compares the differences in phases of the VCO
oscillation frequency and the VCXO reference frequency,
returns the difference to the VCO CV terminal and realizes
the "Phase Locked Loop" for the return control. This allows
the VCO oscillation frequency to accurately match (lock) the
desired frequency.
When the frequency is controlled by the PLL, the
frequency convergence time increases as the frequency
18
CIRCUIT DESCRIPTION
difference increases when the set frequency is changed. To
supplement this, the rheostat is used before control by the
PLL IC to bring the VCO oscillation frequency close to the
desired frequency. As a result, the VCO CV voltage does not
change and is always stable at approx. 2 V.
(IC5) through the 3-line "LE", "DAT", "CLK" serial bus. Whether
the PLL IC is locked or not is monitored by the CPU through
the "UL" signal line. If the VCO is not the desired frequency
(unlock), the "UL" logic is low.
5-5. 1/2 divider (IC304)
1st local receive signal output from the VCO and divides each
frequency by 1/2. The frequency divided by 1/2 becomes a
carrier that is actually sent and a 1st local receive signal that is
actually input to a mixer. (Both the VCO and the PLL IC
operate with double frequencies in phase locked loops.)
5-6. Local Switch (D101, D210)
1/2 divider (IC304) is changed with the diode switch (D101)
that is controlled by the transmission power supply, 5T, and
the diode switch (D210) that is controlled by the receive
power supply, 5R.
pre-drive (Q101). If the 5T logic is low, it is connected to a
receive-side mixer (IC202).
IC5
CPU
6. Control Circuit
circuits. It controls the TX-RX unit and transfers data to the
Control unit. IC5 mainly performs the following;
1) Switching between transmission and reception by PTT
2) Reading system, zone, frequency, and program data from
3) Sending frequency program data to the PLL.
4) Controlling squelch on/off by the DC voltage from the
5) Controlling the audio mute circuit by decode data input.
6) Transmitting tone and encode data.
6-1. Memory Circuit
memory (IC6). A flash memory has a capacity of 16M bits and
The desired frequency is set for the PLL IC by the CPU
The 1/2 divider (IC304) inputs the transmit carrier and the
The connection destination of the signal output from the
If the 5T logic is high, it is connected to a send-side pre-
T/R
PCS
DAT
TX: 272~348MHz
IC414 V-assist
CLK
RX: 371.9~447.9MHz
RHE
LPF VCO
UL CV
IC303 Q312
LPF
PLL BUFF
LE
MOD
DAT
CLK
X301 IC411
VCXO DAC
Fig. 8 PLL block diagram
The control circuit consists of CPU (IC5) and its peripheral
signal input.
the memory circuit.
squelch circuit.
Memory circuit consists of the CPU (IC5) and a flash
to pre-pre-drive
IC304 Q314 D101
(Q101)
1/2 BUFF SW
to 1st mixer
D210
(IC202)
SW