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TQ-Systems TQMLX2160A Preliminary User's Manual page 27

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4.11.4

Pinout TQMLX2160A connectors (continued)

Table 14:

Pinout connector X3 (continued)

CPU ball

Dir.

Level

Group

AV15

I

–

SERDES1

–

–

0 V

Power

AU16

I

–

SERDES1

AT16

I

–

SERDES1

–

–

0 V

Power

AW17

I

–

SERDES1

AV17

I

–

SERDES1

–

–

0 V

Power

–

–

0 V

Power

AP23

I

–

SERDES2

AR23

I

–

SERDES2

–

–

0 V

Power

AW19

I

–

SERDES2

AV19

I

–

SERDES2

–

–

0 V

Power

AU20

I

–

SERDES2

AT20

I

–

SERDES2

–

–

0 V

Power

–

–

0 V

Power

AW21

I

–

SERDES2

AV21

I

–

SERDES2

–

–

0 V

Power

AU22

I

–

SERDES2

AT22

I

–

SERDES2

–

–

0 V

Power

AU24

I

–

SERDES2

AT24

I

–

SERDES2

–

–

0 V

Power

–

–

0 V

Power

AW25

I

–

SERDES2

AV25

I

–

SERDES2

–

–

0 V

Power

AU26

I

–

SERDES2

AT26

I

–

SERDES2

–

–

0 V

Power

AW27

I

–

SERDES2

AV27

I

–

SERDES2

–

–

0 V

Power

–

–

0 V

Power

H7

I/O

1.8 V

GPIO

K7

I/O

1.8 V

GPIO

H8

I/O

1.8 V

GPIO

G5

I/O

3.3 V

F5

O

3.3 V

–

–

0 V

Power

–

–

0 V

Power

–

–

0 V

Power

–

I/O

–

SECURE

–

I/O

–

SECURE

–

–

0 V

Power

–

I/O

3.3 V

SECURE

–

I/O

3.3 V

SECURE

–

O

3.3 V

SECURE

–

I

3.3 V

SECURE

–

–

0 V

Power

Preliminary User's Manual l TQMLX2160A UM 0002 l © 2020, TQ-Systems GmbH

Signal

SD1_RX5_N

DGND

SD1_RX6_P

SD1_RX6_N

DGND

SD1_RX7_P

SD1_RX7_N

DGND

DGND

SD2_PLLF_REFCLK_P

SD2_PLLF_REFCLK_N

DGND

SD2_RX0_P

SD2_RX0_N

DGND

SD2_RX1_P

SD2_RX1_N

DGND

DGND

SD2_RX2_P

SD2_RX2_N

DGND

SD2_RX3_P

SD2_RX3_N

DGND

SD2_RX4_P

SD2_RX4_N

DGND

DGND

SD2_RX5_P

SD2_RX5_N

DGND

SD2_RX6_P

SD2_RX6_N

DGND

SD2_RX7_P

SD2_RX7_N

DGND

DGND

GPIO3_DAT08

GPIO3_DAT09

GPIO3_DAT10

I2C

I2C1_MOD_SDA

I2C

I2C1_MOD_SCL

DGND

DGND

DGND

SE14443_LA

SE14443_LB

DGND

SE_7816_IO1

SE_7816_IO2

SE_7816_CLK

SE_7816_RST#

DGND

Pin

Signal

A56 B56

SD1_TX5_N

A57 B57

DGND

A58 B58

SD1_TX6_P

A59 B59

SD1_TX6_N

A60 B60

DGND

A61 B61

SD1_TX7_P

A62 B62

SD1_TX7_N

A63 B63

DGND

A64 B64

DGND

A65 B65

SD2_PLLS_REFCLK_P

A66 B66

SD2_PLLS_REFCLK_N

A67 B67

DGND

A68 B68

SD2_TX0_P

A69 B69

SD2_TX0_N

A70 B70

DGND

A71 B71

SD2_TX1_P

A72 B72

SD2_TX1_N

A73 B73

DGND

A74 B74

DGND

A75 B75

SD2_TX2_P

A76 B76

SD2_TX2_N

A77 B77

DGND

A78 B78

SD2_TX3_P

A79 B79

SD2_TX3_N

A80 B80

DGND

A81 B81

SD2_TX4_P

A82 B82

SD2_TX4_N

A83 B83

DGND

A84 B84

DGND

A85 B85

SD2_TX5_P

A86 B86

SD2_TX5_N

A87 B87

DGND

A88 B88

SD2_TX6_P

A89 B89

SD2_TX6_N

A90 B90

DGND

A91 B91

SD2_TX7_P

A92 B92

SD2_TX7_N

A93 B93

DGND

A94 B94

DGND

A95 B95

VBAT_RTC

A96 B96

RTC_INT_OUT#

A97 B97

RTC_CLKOUT

A98 B98

EEPROM_WP

A99 B99

EVENT_TEMPSENSOR

A100 B100

DGND

A101 B101

IRQ0

A102 B102

IRQ1

A103 B103

IRQ2

A104 B104

IRQ3

A105 B105

IRQ4

A106 B106

IRQ5

A107 B107

IRQ6

A108 B108

IRQ7

A109 B109

DGND

A110 B110

DGND

Page 22

Group

Level

Dir.

CPU ball

SERDES1

–

O

AN15

Power

0 V

–

SERDES1

–

O

AM16

SERDES1

–

O

Power

0 V

–

SERDES1

–

O

AP17

SERDES1

–

O

AN17

Power

0 V

–

Power

0 V

–

SERDES2

–

I

AV23

SERDES2

–

I

AW23

Power

0 V

–

SERDES2

–

O

AP19

SERDES2

–

O

AN19

Power

0 V

–

SERDES2

–

O

AM20

SERDES2

–

O

Power

0 V

–

Power

0 V

–

SERDES2

–

O

AP21

SERDES2

–

O

AN21

Power

0 V

–

SERDES2

–

O

AM22

SERDES2

–

O

Power

0 V

–

SERDES2

–

O

AM24

SERDES2

–

O

Power

0 V

–

Power

0 V

–

SERDES2

–

O

AP25

SERDES2

–

O

AN25

Power

0 V

–

SERDES2

–

O

AM26

SERDES2

–

O

Power

0 V

–

SERDES2

–

O

AP27

SERDES2

–

O

AN27

Power

0 V

–

Power

0 V

–

RTC

3.3 V

I

RTC

3.3 V

O

RTC

3.3 V

O

EEPROM

3.3 V

I

TEMP

3.3 V

O

Power

0 V

–

IRQ

1.8 V

I/O

IRQ

1.8 V

I/O

IRQ

1.8 V

I/O

IRQ

1.8 V

I/O

IRQ

1.8 V

I/O

IRQ

1.8 V

I/O

IRQ

1.8 V

I/O

IRQ

1.8 V

I/O

Power

0 V

–

Power

0 V

–

–

AL16

–

–

–

–

–

AL20

–

–

–

AL22

–

AL24

–

–

–

AL26

–

–

–

–

–

–

–

–

–

H9

H10

11

J7

J11

J9

H6

K6

–

–

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