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4.11.2
SerDes track length
The following table shows the SerDes interface track lengths on the TQMLX2160A from the CPU ball to the connector pin,
and the insertion loss of each lane in dB assuming the following conditions:
• PCIe Gen 3:
4.00 GHz
• XFI:
5.17 GHz
• CAUI:
12.90 GHz
Table 11:
SerDes track length and estimated insertion loss
SerDes
Lane
Lane 0
Lane 1
Lane 2
Lane 3
SerDes 1
Lane 4
Lane 5
Lane 6
Lane 7
Lane 0
Lane 1
Lane 2
Lane 3
SerDes 2
Lane 4
Lane 5
Lane 6
Lane 7
Lane 0
Lane 1
Lane 2
Lane 3
SerDes 3
Lane 4
Lane 5
Lane 6
Lane 7
Preliminary User's Manual l TQMLX2160A UM 0002 l © 2020, TQ-Systems GmbH
Signal
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
PLLF
–
PLLS
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
PLLF
–
PLLS
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
PLLF
–
PLLS
Length (mm)
PCIe Gen 3 (dB)
19.7
0.42
19.1
0.41
21.5
0.45
20.9
0.44
19.5
0.42
18.8
0.41
21.4
0.45
20.8
0.44
21.4
0.45
20.8
0.44
19.2
0.41
18.9
0.41
21.6
0.45
20.6
0.44
19.5
0.42
18.6
0.40
30.1
–
23.5
–
19.9
0.42
19.1
0.41
22.0
0.46
21.3
0.45
19.9
0.42
19.9
0.42
22.4
0.47
21.9
0.46
22.2
0.46
21.7
0.46
19.9
0.42
19.5
0.42
22.2
0.46
21.8
0.46
20.0
0.43
20.0
0.43
25.7
–
16.9
–
27.2
0.47
25.5
0.52
27.8
0.56
26.6
0.54
26.0
0.53
25.1
0.51
28.3
0.57
28.0
0.57
27.6
0.56
27.1
0.55
25.9
0.53
26.7
0.54
28.2
0.57
28.3
0.57
26.1
0.53
26.8
0.54
25.2
–
26.0
–
Page 16
XFI (dB)
CAUI (dB)
0.49
0.95
0.48
0.93
0.52
1.01
0.51
0.99
0.48
0.94
0.47
0.92
0.52
1.01
0.51
0.99
0.52
1.01
0.51
0.99
0.48
0.93
0.47
0.93
0.53
1.01
0.51
0.98
0.48
0.94
0.47
0.92
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.54
–
0.53
–
0.49
–
0.49
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
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