4.11.4
Pinout TQMLX2160A connectors (continued)
Table 13:
Pinout connector X2 (continued)
CPU ball
Dir.
Level
Group
D10
I
–
USB2
–
–
0 V
Power
F10
I/O
–
USB2
F11
I/O
–
USB2
–
–
0 V
Power
–
–
0 V
Power
F17
I
–
SERDES3
E17
I
–
SERDES3
–
–
0 V
Power
F13
O
–
SERDES3
G13
O
–
SERDES3
–
–
0 V
Power
H14
O
–
SERDES3
J14
O
–
SERDES3
–
–
0 V
Power
–
–
0 V
Power
F15
O
–
SERDES3
G15
O
–
SERDES3
–
–
0 V
Power
H16
O
–
SERDES3
J16
O
–
SERDES3
–
–
0 V
Power
H18
O
–
SERDES3
J18
O
–
SERDES3
–
–
0 V
Power
–
–
0 V
Power
F19
O
–
SERDES3
G19
O
–
SERDES3
–
–
0 V
Power
H20
O
–
SERDES3
J20
O
–
SERDES3
–
–
0 V
Power
F21
O
–
SERDES3
G21
O
–
SERDES3
–
–
0 V
Power
–
–
0 V
Power
A25
I/O
1.8 V
SDHC_2
–
–
0 V
Power
C25
I/O
1.8 V
SDHC_2
–
–
0 V
Power
B25
I/O
1.8 V
SDHC_2
–
–
0 V
Power
–
–
0 V
Power
–
–
0 V
Power
–
–
0 V
Power
–
I
3.3 V
CONFIG
–
I
3.3 V
CONFIG
–
I
3.3 V
CONFIG
–
I
3.3 V
CONFIG
–
I
3.3 V
CONFIG
–
–
0 V
Power
D27
I/O
1.8 V
C27
I/O
1.8 V
–
O
1.8 V
JTAG_CPU
–
–
0 V
Power
Preliminary User's Manual l TQMLX2160A UM 0002 l © 2020, TQ-Systems GmbH
Signal
USB2_RX_N
DGND
USB2_DP
USB2_DN
DGND
DGND
SD3_PLLF_REFCLK_P
SD3_PLLF_REFCLK_N
DGND
SD3_TX0_P
SD3_TX0_N
DGND
SD3_TX1_P
SD3_TX1_N
DGND
DGND
SD3_TX2_P
SD3_TX2_N
DGND
SD3_TX3_P
SD3_TX3_N
DGND
SD3_TX4_P
SD3_TX4_N
DGND
DGND
SD3_TX5_P
SD3_TX5_N
DGND
SD3_TX6_P
SD3_TX6_N
DGND
SD3_TX7_P
SD3_TX7_N
DGND
DGND
SDHC_2_MOD_CLK
DGND
SDHC_2_MOD_DS
DGND
SDHC_2_MOD_CMD
DGND
DGND
DGND
DGND
LX_CONFIG_RFU1
LX_CONFIG_RFU2
LX_CONFIG_RFU3
LX_CONFIG_RFU4
LX_CONFIG_RFU5
DGND
I2C
I2C6_CPU_SCL
I2C
I2C5_CPU_SDA
JTAG_LX_VREF
DGND
Pin
Signal
A56 B56
DGND
A57 B57
USB2_PWRFAULT
A58 B58
USB2_DRVBUS
A59 B59
USB2_VBUS
A60 B60
DGND
A61 B61
DGND
A62 B62
SD3_PLLS_REFCLK_P
A63 B63
SD3_PLLS_REFCLK_N
A64 B64
DGND
A65 B65
SD3_RX0_P
A66 B66
SD3_RX0_N
A67 B67
DGND
A68 B68
SD3_RX1_P
A69 B69
SD3_RX1_N
A70 B70
DGND
A71 B71
DGND
A72 B72
SD3_RX2_P
A73 B73
SD3_RX2_N
A74 B74
DGND
A75 B75
SD3_RX3_P
A76 B76
SD3_RX3_N
A77 B77
DGND
A78 B78
SD3_RX4_P
A79 B79
SD3_RX4_N
A80 B80
DGND
A81 B81
DGND
A82 B82
SD3_RX5_P
A83 B83
SD3_RX5_N
A84 B84
DGND
A85 B85
SD3_RX6_P
A86 B86
SD3_RX6_N
A87 B87
DGND
A88 B88
SD3_RX7_P
A89 B89
SD3_RX7_N
A90 B90
DGND
A91 B91
DGND
A92 B92
SDHC_2_MOD_DAT0
A93 B93
SDHC_2_MOD_DAT1
A94 B94
SDHC_2_MOD_DAT2
A95 B95
SDHC_2_MOD_DAT3
A96 B96
SDHC_2_MOD_DAT4
A97 B97
SDHC_2_MOD_DAT5
A98 B98
SDHC_2_MOD_DAT6
A99 B99
SDHC_2_MOD_DAT7
A100 B100
DGND
A101 B101
DGND
A102 B102
TBSCAN_EN#
A103 B103
DGND
A104 B104
JTAG_LX_HRESET
A105 B105
JTAG_LX_TDI
A106 B106
JTAG_LX_TDO
A107 B107
JTAG_LX_TMS
A108 B108
JTAG_LX_TRST#
A109 B109
JTAG_LX_TCK
A110 B110
DGND
Page 20
Group
Level
Dir.
CPU ball
Power
0 V
–
USB2
1.8 V
I/O
USB2
1.8 V
I/O
USB2
5 V
I
Power
0 V
–
Power
0 V
–
SERDES3
–
I
SERDES3
–
I
Power
0 V
–
SERDES3
–
I
SERDES3
–
I
Power
0 V
–
SERDES3
–
I
SERDES3
–
I
Power
0 V
–
Power
0 V
–
SERDES3
–
I
SERDES3
–
I
Power
0 V
–
SERDES3
–
I
SERDES3
–
I
Power
0 V
–
SERDES3
–
I
SERDES3
–
I
Power
0 V
–
Power
0 V
–
SERDES3
–
I
SERDES3
–
I
Power
0 V
–
SERDES3
–
I
SERDES3
–
I
Power
0 V
–
SERDES3
–
I
SERDES3
–
I
Power
0 V
–
Power
0 V
–
SDHC_2
1.8 V
I/O
SDHC_2
1.8 V
I/O
SDHC_2
1.8 V
I/O
SDHC_2
1.8 V
I/O
SDHC_2
1.8 V
I/O
SDHC_2
1.8 V
I/O
SDHC_2
1.8 V
I/O
SDHC_2
1.8 V
I/O
Power
0 V
–
Power
0 V
–
TEST
1.8 V
I
Power
0 V
–
JTAG_CPU
1.8 V
I
JTAG_CPU
1.8 V
I
JTAG_CPU
1.8 V
O
JTAG_CPU
1.8 V
I
JTAG_CPU
1.8 V
I
JTAG_CPU
1.8 V
I
Power
0 V
–
–
G7
E7
G10
–
–
B17
A17
–
A13
B13
–
C14
D14
–
–
A15
B15
–
C16
D16
–
C18
D18
–
–
A19
B19
–
C20
D20
–
A21
B21
–
–
A23
C24
B23
A24
C26
B27
A26
A27
–
–
F23
–
–
H27
G27
G25
H26
G26
–
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