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TQ-Systems TQMLX2160A Preliminary User's Manual page 26

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4.11.4

Pinout TQMLX2160A connectors (continued)

Table 14:

Pinout connector X3

CPU ball

Dir.

Level

Group

–

–

0 V

Power

J4

I/O

1.8 V

–

–

0 V

Power

J3

I/O

1.8 V

H3

I/O

1.8 V

G4

I/O

1.8 V

G3

I/O

1.8 V

–

–

0 V

Power

F3

I/O

1.8 V

–

–

0 V

Power

–

–

0 V

Power

N4

I/O

1.8 V

–

–

0 V

Power

N3

I/O

1.8 V

M3

I/O

1.8 V

L4

I/O

1.8 V

L3

I/O

1.8 V

–

–

0 V

Power

K3

I/O

1.8 V

–

–

0 V

Power

–

–

0 V

Power

R2

O

1.8 V

R1

I/O

1.8 V

–

–

0 V

Power

P4

O

1.8 V

R3

I/O

1.8 V

–

–

0 V

Power

K9

I/O

1.8 V

L11

I/O

1.8 V

G6

I/O

1.8 V

–

–

0 V

Power

L10

I/O

1.8 V

–

–

0 V

Power

–

–

0 V

Power

–

–

0 V

Power

AW13

I

–

SERDES1

AV13

I

–

SERDES1

–

–

0 V

Power

AW9

I

–

SERDES1

AV9

I

–

SERDES1

–

–

0 V

Power

AU10

I

–

SERDES1

AT10

I

–

SERDES1

–

–

0 V

Power

AW11

I

–

SERDES1

AV11

I

–

SERDES1

–

–

0 V

Power

AU12

I

–

SERDES1

AT12

I

–

SERDES1

–

–

0 V

Power

–

–

0 V

Power

AU14

I

–

SERDES1

AT14

I

–

SERDES1

–

–

0 V

Power

AW15

I

–

SERDES1

Preliminary User's Manual l TQMLX2160A UM 0002 l © 2020, TQ-Systems GmbH

Signal

DGND

EC1

EC1_TX_EN

DGND

EC1

EC1_TXD0

EC1

EC1_TXD1

EC1

EC1_TXD2

EC1

EC1_TXD3

DGND

EC1

EC1_GTX_CLK

DGND

DGND

EC2

EC2_TX_EN

DGND

EC2

EC2_TXD0

EC2

EC2_TXD1

EC2

EC2_TXD2

EC2

EC2_TXD3

DGND

EC2

EC2_GTX_CLK

DGND

DGND

EMI

EMI1_MDC

EMI

EMI1_MDIO

DGND

EMI

EMI2_MDC

EMI

EMI2_MDIO

DGND

EVT

EVT0#

EVT

EVT1#

EVT

EVT2#

DGND

EVT

EVT3#

DGND

DGND

DGND

SD1_PLLF_REFCLK_P

SD1_PLLF_REFCLK_N

DGND

SD1_RX0_P

SD1_RX0_N

DGND

SD1_RX1_P

SD1_RX1_N

DGND

SD1_RX2_P

SD1_RX2_N

DGND

SD1_RX3_P

SD1_RX3_N

DGND

DGND

SD1_RX4_P

SD1_RX4_N

DGND

SD1_RX5_P

Pin

Signal

A1

B1

DGND

A2

B2

EC1_RX_CLK

A3

B3

DGND

A4

B4

EC1_RXD0

A5

B5

EC1_RXD1

A6

B6

EC1_RXD2

A7

B7

EC1_RXD3

A8

B8

EC1_RX_DV

A9

B9

DGND

A10 B10

DGND

A11 B11

DGND

A12 B12

EC2_RX_CLK

A13 B13

DGND

A14 B14

EC2_RXD0

A15 B15

EC2_RXD1

A16 B16

EC2_RXD2

A17 B17

EC2_RXD3

A18 B18

EC2_RX_DV

A19 B19

DGND

A20 B20

DGND

A21 B21

DGND

A22 B22

EC_GTX_CLK125_IN_P

A23 B23

EC_GTX_CLK125_IN_N

A24 B24

DGND

A25 B25

CLK_OUT

A26 B26

DGND

A27 B27

CAN1_TX

A28 B28

CAN1_RX

A29 B29

CAN2_TX

A30 B30

CAN2_RX

A31 B31

DGND

A32 B32

EVT4#

A33 B33

DGND

A34 B34

DGND

A35 B35

DGND

A36 B36

SD1_PLLS_REFCLK_P

A37 B37

SD1_PLLS_REFCLK_N

A38 B38

DGND

A39 B39

SD1_TX0_P

A40 B40

SD1_TX0_N

A41 B41

DGND

A42 B42

SD1_TX1_P

A43 B43

SD1_TX1_N

A44 B44

DGND

A45 B45

SD1_TX2_P

A46 B46

SD1_TX2_N

A47 B47

DGND

A48 B48

SD1_TX3_P

A49 B49

SD1_TX3_N

A50 B50

DGND

A51 B51

DGND

A52 B52

SD1_TX4_P

A53 B53

SD1_TX4_N

A54 B54

DGND

A55 B55

SD1_TX5_P

Page 21

Group

Level

Dir.

CPU ball

Power

0 V

–

EC1

1.8 V

I/O

Power

0 V

–

EC1

1.8 V

I/O

EC1

1.8 V

I/O

EC1

1.8 V

I/O

EC1

1.8 V

I/O

EC1

1.8 V

I/O

Power

0 V

–

Power

0 V

–

Power

0 V

–

EC2

1.8 V

I/O

Power

0 V

–

EC2

1.8 V

I/O

EC2

1.8 V

I/O

EC2

1.8 V

I/O

EC2

1.8 V

I/O

EC2

1.8 V

I/O

Power

0 V

–

Power

0 V

–

Power

0 V

–

EC1

–

I

EC1

–

I

Power

0 V

–

CLKOUT

1.8 V

I/O

Power

0 V

–

CAN

1.8 V

I/O

CAN

1.8 V

I/O

CAN

1.8 V

I/O

CAN

1.8 V

I/O

Power

0 V

–

EVT

1.8 V

I/O

Power

0 V

–

Power

0 V

–

Power

0 V

–

SERDES1

–

I

AR13

SERDES1

–

I

AP13

Power

0 V

–

SERDES1

–

O

SERDES1

–

O

Power

0 V

–

SERDES1

–

O

AM10

SERDES1

–

O

Power

0 V

–

SERDES1

–

O

AP11

SERDES1

–

O

AN11

Power

0 V

–

SERDES1

–

O

AM12

SERDES1

–

O

Power

0 V

–

Power

0 V

–

SERDES1

–

O

AM14

SERDES1

–

O

Power

0 V

–

SERDES1

–

O

AP15

–

G1

–

J2

J1

H1

G2

K1

–

–

–

L1

–

N2

N1

M1

L2

P1

–

–

–

–

–

–

L6

–

H5

J5

K5

L5

–

M10

–

–

–

–

AP9

AN9

–

AL10

–

–

AL12

–

–

AL14

–

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