Reset Structure; Boot Source; Ddr4 Sdram - TQ-Systems TQMLX2160A Preliminary User's Manual

4.2

Reset structure

The following block diagram illustrates the Reset circuitry on the TQMLX2160A.
LX2160A
RESET_REQ#
RESET
HRESET#
PORESET#
TRST_CPU#
Figure 5: Block diagram Reset structure
4.3

Boot source

The boot source of the TQMLX2160A is selected with signals BOOT_SRC[2:0]. Pull-Ups to 3.3 V are provided on the TQMLX2160A.
Table 2: Boot source selection
BOOT_SRC2 (X2-A34)
1
1
1
1
0
0
0
0
4.4

DDR4 SDRAM

The LX2160A features two DDR4 controllers. Both controllers have a 72 bit interface (64 bit + 8 bit ECC) each.
ECC is an assembly option and is assembled as an additional DDR4 SDRAM device.
Up to 64 Gbyte of DDR4 SDRAM with a transfer rate of 2800 MT/s can be assembled on the TQMLX2160A.
Preliminary User's Manual l TQMLX2160A UM 0002 l © 2020, TQ-Systems GmbH
System
BOOT_SRC1 (X2-A33)
1
1
0
0
1
1
0
0
BOOT_SRC0 (X2-A32)
1
0
1
0
1
0
1
0
RESET_REQ_OUT#
HRESET_OUT#
LX_CPU_RESET_OUT#
Status
LED
TQMLX_RST#
HRESET_IN#
JTAG_TRST#
Boot source
NOR flash
SD card
eMMC
I²C
XSPI – NAND 2 KB
Undefined
Hard Coded Option 0x01
Hard Coded Option 0x02
Page 7
Module
Connector