TQ-Systems TQMLX2160A Preliminary User's Manual page 24

4.11.4 Pinout TQMLX2160A connectors (continued)
Table 13: Pinout connector X2
CPU ball Dir. Level Group
– – 0 V Power
– O 3.3 V Reset
M9 O 3.3 V Reset
F6 O 3.3 V Reset
– – 0 V Power
F5 I/O 1.8 V
G5 I/O 1.8 V
– – 0 V Power
– I 3.3 V JTAG_CPLD
– I 3.3 V JTAG_CPLD
– – 0 V Power
– O 3.3 V JTAG_CPLD
– I 3.3 V JTAG_CPLD
– – 0 V Power
– I 3.3 V SYSC
– I/O 3.3 V SYSC
– – 0 V Power
– – 0 V Power
E3 I/O 1.8 V SDHC_1
E4 I/O 1.8 V SDHC_1
– – 0 V Power
D1 I/O EVDD SDHC_1
– – 0 V Power
B2 I/O 1.8 V SDHC_1
– – 0 V Power
E1 I/O EVDD SDHC_1
– – 0 V Power
– I 3.3 V CONFIG
– I 3.3 V CONFIG
– – 0 V Power
– – 0 V Power
– I 3.3 V CONFIG
– I 3.3 V CONFIG
– I 3.3 V CONFIG
– – 0 V Power
– I 3.3 V CONFIG
– – 0 V Power
– I 1.8 V CONFIG
– O 3.3 V SYSC
– I/O 3.3 V SYSC
– – 0 V Power
– – 0 V Power
A9 O – USB1
B9 O – USB1
– – 0 V Power
C8 I – USB1
D8 I – USB1
– – 0 V Power
F8 I/O – USB1
F9 I/O – USB1
– – 0 V Power
A11 O – USB2
B11 O – USB2
– – 0 V Power
C10 I – USB2
Preliminary User's Manual l TQMLX2160A UM 0002 l © 2020, TQ-Systems GmbH
Signal
DGND
LX_CPU_RESET_OUT#
RESET_REQ_OUT
HRESET_OUT#
DGND
I2C I2C1_CPU_SCL
I2C I2C2_CPU_SDA
DGND
JTAG_CPLD_TCK
JTAG_CPLD_TMS
DGND
JTAG_CPLD_TDO
JTAG_CPLD_TDI
DGND
SYSC_SWCLK
SYSC_SWDIO
DGND
DGND
SDHC_1_CD#
SDHC_1_WP
DGND
SDHC_1_CLK
DGND
SDHC_1_DS
DGND
SDHC_1_CMD
DGND
eMMC_SEL0
eMMC_SEL1
DGND
DGND
BOOT_SRC0
BOOT_SRC1
BOOT_SRC2
DGND
NOR_SWAP#
DGND
EVDD_SEL
SYSC_I2C2_SCL
SYSC_I2C2_SDA
DGND
DGND
USB1_TX_P
USB1_TX_N
DGND
USB1_RX_P
USB1_RX_N
DGND
USB1_DP
USB1_DN
DGND
USB2_TX_P
USB2_TX_N
DGND
USB2_RX_P
Pin Signal
A1 B1 DGND
A2 B2 TQMLX_RST_IN#
A3 B3 SYSC_MON_UART_RX
A4 B4 SYSC_MON_UART_TX
A5 B5 DGND
A6 B6 SYSC_UART_MUX_RX
A7 B7 SYSC_UART_MUX_TX
A8 B8 DGND
A9 B9 I2C5_CPU_SCL
A10 B10 I2C5_CPU_SDA
A11 B11 DGND
A12 B12 UART1_SOUT
A13 B13 UART1_SIN
A14 B14 UART2_SOUT
A15 B15 UART2_SIN
A16 B16 UART3_SOUT
A17 B17 UART3_SIN
A18 B18 UART4_SOUT
A19 B19 UART4_SIN
A20 B20 DGND
A21 B21 DGND
A22 B22 SDHC_1_DAT0
A23 B23 SDHC_1_DAT1
A24 B24 SDHC_1_DAT2
A25 B25 SDHC_1_DAT3
A26 B26 SDHC_1_DAT4
A27 B27 SDHC_1_DAT5
A28 B28 SDHC_1_DAT6
A29 B29 SDHC_1_DAT7
A30 B30 DGND
A31 B31 DGND
A32 B32 DGND
A33 B33 DGND
A34 B34 DGND
A35 B35 TA_BB_TMP_DETECT#
A36 B36 TA_TMP_DETECT#
A37 B37 TQMLX_WAKE
A38 B38 TQMLX_SLEEP#
A39 B39 EXT_POWER_FAIL_IN#
A40 B40 TQMLX_PGOOD
A41 B41 DGND
A42 B42 DGND
A43 B43 DGND
A44 B44 DGND
A45 B45 USB1_ID
A46 B46 DGND
A47 B47 DGND
A48 B48 USB1_PWRFAULT
A49 B49 USB1_DRVBUS
A50 B50 USB1_VBUS
A51 B51 DGND
A52 B52 DGND
A53 B53 DGND
A54 B54 USB2_ID
A55 B55 DGND
Page 19
Group Level Dir. CPU ball
Power 0 V –
Reset 3.3 V I
SYSC 3.3 V I
SYSC 3.3 V O
Power 0 V –
SYSC 3.3 V I
SYSC 3.3 V O
Power 0 V –
I2C 1.8 V I/O
I2C 1.8 V I/O
Power 0 V –
UART 1.8 V I/O
UART 1.8 V I/O
UART 1.8 V I/O
UART 1.8 V I/O
UART 1.8 V I/O
UART 1.8 V I/O
UART 1.8 V I/O
UART 1.8 V I/O
Power 0 V –
Power 0 V –
SDHC_1 EVDD I/O
SDHC_1 EVDD I/O
SDHC_1 EVDD I/O
SDHC_1 EVDD I/O
SDHC_1 1.8 V I/O
SDHC_1 1.8 V I/O
SDHC_1 1.8 V I/O
SDHC_1 1.8 V I/O
Power 0 V –
Power 0 V –
Power 0 V –
Power 0 V –
Power 0 V –
TRUST I
TA_BB_VDD
TRUST 1.8 V I
CONFIG 3.3 V I
CONFIG 3.3 V I
CONFIG 3.3 V I
CONFIG 3.3 V O
Power 0 V –
Power 0 V –
Power 0 V –
Power 0 V –
USB1 3.3 V I/O
Power 0 V –
Power 0 V –
USB1 1.8 V I/O
USB1 1.8 V I/O
USB1 5 V I
Power 0 V –
Power 0 V –
Power 0 V –
USB2 3.3 V IO
Power 0 V –
–
–
–
–
–
–
–
–
C4
D3
–
B6
B5
D6
D5
A5
A6
C5
C6
–
–
F1
E2
C1
C2
A3
A4
B3
C3
–
–
–
–
–
J27
N9
–
–
–
–
–
–
–
–
E9
–
–
B7
A7
G8
–
–
–
E11
–