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I.L. 40-386.3
AND-51, AND-50, OR-18, and AND-35, sending a blocking signal to the other
terminals. The local receiver receives the blocking signal, disables the operation
of AND-47; therefore, AND-48 will produce no carrier trip signal for AND-52.
b. Carrier Keying Logic
3)
Reverse fault keying (Figure 2-24)
For a reverse fault, the ∆I and ∆V as well as the local reverse-looking relay
4)
Zone3Ø)(R)/Z3G(R) or RDOG sees the fault, operates the CARSND relay and
starts the transmitter, sending a blocking signal to the other terminals.
NOTE: The use of ∆I and ∆V for carrier start provides more security to the block-
1)
This keying circuit includes logic OR-50A, AND-50, AND-173, OR-41, AND-51,
OR-18 and AND-35. The logic of AND -50B and the 32/0 ms timer circuit stops
the internal fault "SEND" on a weakfeed condition.
2)
Since the present keying practice on (OUT) system uses either the contact open
(negative or positive removal keying) or contact close (positive keying) approach,
a form-C dry contact output for keying is provided in REL 302.
3)
Signal continuation and TBM logic
4)
For a reverse fault, both the local carrier start relay(s) and the remote pilot re-
lay(s) see the fault and operate. The local carrier start relay(s) start the carrier
and send a blocking signal to block the remote pilot relay from tripping. After the
fault is cleared by the external breaker, the remote breaker may have a tendency
to trip falsely if the carrier start unit resets faster than the pilot trip unit. The 0/
50 ms timer between the OR-41 and AND-51 holds the carrier signal for 50 ms
after the carrier start units have been reset for improving this problem. This logic
also provides transient block and unblock (TBM) effect on power reversal.
5)
The subsequent out-of-step condition, as described in Section 3.4.17.1, may
cause the reverse looking units to fail to operate on external faults, and intro-
duce false pilot tripping at the other end. Enhanced logic has been added to the
design as shown in Figure 2-24, which includes OR-41C, 32/0 ms timer, AND-
41B and OR-41. It utilizes the not FDOP (or FDOG) and LV condition (LV units
can be set between 40 and 60 volts) to initiate the TBM circuit; and sends a
blocking signal to the remote end. Set OS Block to YES for supervising AND-41B
when this enhanced logic is required in the application. Set Weakfeed to YES if
this terminal may become a weakfeed condition.
6)
Internal fault preference and squelch
7)
On a close-in fault, the carrier start unit may operate and start the transmitter.
This operation may block the system from pilot tripping. The negating signal
from OR-16 to AND-50 will provide an internal fault preference feature for solv-
ing this problem. The squelch 0/150 ms timer is required for improving the
problem if the local breaker tripped faster than the remote breaker on an inter-
nal fault. The logic holds the carrier key circuit on the "stop" mode for 150 ms
after any high speed tripping, including pilot trip, Zone1 trip and instantaneous
overcurrent trip.
2-18
ing scheme.
(10/94)
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