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Optimizer Mode
This mode supports Single Device Data Correction (SDDC) only for memory modules that use x4 device width. It does not
impose any specific slot population requirements.
● Dual processor: Populate the slots in round robin sequence starting with processor 1.
NOTE:
Processor 1 and processor 2 population should match.
● Quad processor: Populate the slots in round robin sequence starting with processor 1.
NOTE:
Processor 1, processor 2, processor 3, and processor 4 population should match.
Table 11. Memory population rules
Processor
Configuration
Dual processor (Start
Optimized (Independent
with processor1.
channel) population order
processor1 and
processor 2
population should
match)
Mirroring population
order
Single rank sparing
population order
Multi rank sparing
population order
Fault resilient population
order
Quad processor
Optimized population
(Starting with
order (Independent
processor 1, and
channel)
processor 1,
Memory population
A{1}, B{1},
A{2}, B{2},
A{3}, B{3},
A{4}, B{4},
A{5}, B{5},
A{6}, B{6}
A{1, 2, 3, 4, 5, 6},
B{1, 2, 3, 4, 5, 6},
A{7, 8, 9, 10, 11, 12},
B{7, 8, 9, 10, 11, 12}
A{1}, B{1},
A{2}, B{2},
A{3}, B{3},
A{4}, B{4},
A{5}, B{5},
A{6}, B{6}
A{1}, B{1},
A{2}, B{2},
A{3}, B{3},
A{4}, B{4},
A{5}, B{5},
A{6}, B{6}
A{1, 2, 3, 4, 5, 6},
B{1, 2, 3, 4, 5, 6},
A{7, 8, 9, 10, 11, 12},
B{7, 8, 9, 10, 11, 12}
A{1}, B{1}, C{1}, D{1},
A{2}, B{2}, C{2}, D{2},
Installing and removing sled components
Memory population information
Odd number of DIMM population per processor
is allowed.
NOTE:
Odd number of DIMMs will result in
unbalanced memory configurations, which
in turn will result in performance loss. It is
recommended to populate all memory
channels identically with identical DIMMs
for best performance.
NOTE:
For best performance, 6 DIMMs or
12 DIMMs per processor is recommended.
Optimizer population order is not traditional for
8 and 16 DIMMs installations for dual processor.
● For 8 DIMMs: A1, A2, A4, A5, B1, B2, B4, B5
● For 16 DIMMs:
A1, A2, A4, A5, A7, A8, A10, A11
B1, B2, B4, B5, B7, B8, B10, B11
Mirroring is supported with 6 or 12 DIMMs per
processor.
● DIMMs must be populated in the order
specified.
● Requires two ranks or more per channel.
● DIMMs must be populated in the order
specified.
● Requires three ranks or more per channel.
Supported with 6 or 12 DIMMs per processor.
Odd number of DIMM population per processor
is allowed.
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