Dell EMC PowerEdge MX740c Installation And Service Manual page 47

● NVDIMM-Ns or RDIMMs must not be mixed with LRDIMMs.
● DDR4 NVDIMM-Ns must be populated only on the black release tabs on processor 1 and 2.
● All slots on configurations 3, 6, 9, and 12 can be used, but a maximum of 12 NVDIMM-Ns can be installed in a system.
NOTE: NVDIMM-N memory slots are not hot-pluggable.
For more information about the supported NVDIMM-N configurations, see the NVDIMM-N User Guide at
poweredgemanuals.
Table 5. Supported NVDIMM-N for dual processor configurations
Configuration
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Configuration 5
Configuration 6
Configuration 7
Configuration 8
Configuration 9
Configuration 10
Configuration 11
Description
12x 16 GB RDIMMs, 1x
NVDIMM-N
12x 32 GB RDIMMs, 1x
NVDIMM-N
23x 32 GB RDIMMs, 1x
NVDIMM-N
12x 16 GB RDIMMs, 2x
NVDIMM-Ns
12x 32 GB RDIMMs, 2x
NVDIMM-Ns
22x 32 GB RDIMMs, 2x
NVDIMM-Ns
12x 16 GB RDIMMs, 4x
NVDIMM-Ns
22x 32 GB RDIMMs, 4x
NVDIMM-Ns
20x 32 GB RDIMMs, 4x
NVDIMM-Ns
12x 16 GB RDIMMs, 6x
NVDIMM-Ns
12x 32 GB RDIMMs, 6x
NVDIMM-Ns
Memory population rules
RDIMMs
Processor1 {A1, 2, 3, 4, 5, 6}
Processor2 {B1, 2, 3, 4, 5, 6}
Same for all 12x RDIMM
configurations. See
Configuration 1.
Processor1 {A1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12}
Processor2 {B1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11}
Same for all 12x RDIMM
configurations. See
Configuration 1.
Same for all 12x RDIMM
configurations. See
Configuration 1.
Processor1 {A1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11}
Processor2 {B1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11}
Same for all 12x RDIMM
configurations. See
Configuration 1.
Same for all 12x RDIMM
configurations. See
Configuration 1.
Processor1 {A1, 2, 3, 4, 5, 6, 7,
8, 9, 10}
Processor2 {B1, 2, 3, 4, 5, 6,
7, 8, 9, 10}
Same for all 12x RDIMM
configurations. See
Configuration 1.
Same for all 12x RDIMM
configurations. See
Configuration 1.
Installing and removing system components
www.dell.com/
NVDIMM-N
Processor1 {A7}
Processor1 {A7}
Processor2 {B12}
Processor1 {A7}
Processor2 {B7}
Processor1 {A7}
Processor2 {B7}
Processor1 {A12}
Processor2 {B12}
Processor1 {A7, A8}
Processor2 {B7, B8}
Processor1 {A7, A8}
Processor2 {B7, B8}
Processor1 {A11, 12}
Processor2 {B11, 12}
Processor1 {A7, 8, 9}
Processor2 {B7, 8, 9}
Processor1 {A7, 8, 9}
Processor2 {B7, 8, 9}
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