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PCI,
Continued
PCI Features
is processor-independent,
•
has a multiplexed address, command, and data bus and supports burst mode operation on reads and
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writes,
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runs synchronous with the CPU at speeds up to 33 MHz,
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has a maximum data transfer rate of 120 MBs (with a peak rate of 132 MBs on a 32-bit data path),
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has a maximum data transfer rate of 240 MBs (with a peak rate of 264 MBs on a 64-bit data path),
has an optional 64-bit data path that is transparently interoperable with the 32-bit data path,
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has low latency random accesses (about 60 ns write access latency) to slave registers from a PCI bus
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master on the PCI bus,
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is capable of full concurrency with the processor and PCI bus masters,
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has full multimaster capability, allowing any PCI Master peer-to-peer access to any PCI slave,
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has hidden and overlapped central arbitration,
has a low pin count (master - 47; slave - 45),
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has address and data parity, and
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uses three physical address spaces: 32-bit memory, 32-bit I/O, and a 256 byte-per-agent configuration
•
space.
Chapter 3 PCI
12
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