Headstage Test Dongle - imec NEUROPIXELS 1.0 User Manual

This can serve as an input to connect an external digital trigger signal to start data
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acquisition, or it can serve as an output to indicate the occurrence of an internal trigger
such as a software trigger, a user-defined data trigger, or a trigger from the PXI backplane
trigger bus (another PXIe acquisition module or card in the PXIe chassis).
It can serve as an input for an external SYNC signal, or it can serve as an output for an
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internal SYNC signal. This SYNC signal is recorded with neural data across all probes
connected to the chassis and can be used to align neural data over different probes in
time. When used as an output for the internal trigger signal, a 1 ms pulse is generated on
the SMA. When used as an input, a pulse with a minimum width of 16 ns must be
connected.
The use and polarity of the SYNC/TRIGGER signal is configured using API functions. The
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SYNC/TRIGGER line is compatible with 5.0 V logic signals. When used as an output
(software trigger or SYNC output), a high impedance load must be connected to the SMA
connector to observe the SYNC/TRIGGER output.
An EEPROM contains the serial number, part number, version and revision number of the PXIe
acquisition module. While the PXIe module contains hardware provisions for an ethernet connection,
neither FPGA code nor API currently support this functionality.
NOTE: Please carefully read and follow the instructions on ESD protection (Appendix C) prior to
handling any system components.

3.5 Headstage Test Dongle

The HS test dongle (HST) is a small test box (Figure 10) that plugs into the HS ZIF connector of a
headstage. Its purpose is to help verify the functionality of a HS. This is useful when e.g. neural data
seems corrupted or cannot be recorded or when a probe cannot be programmed correctly anymore.
Figure 10: Headstage test dongle with flex cable that plugs into the ZIF connector of a headstage.
Verifying the HS functionality is one of the first steps when identifying the root cause(s) for observed
failures. The HS tests will be integrated in the application software (Open Ephys, SpikeGLX). In case of
failure, the application can provide more detailed information about the exact source of the failure (e.g.
power supply, serial data link, clock signal, reset signals, etc. LEDs on the HST indicate status and result
of the HS tests. We recommend to always repeat the HS test also with an un-used, good HS to verify
that the failure is not related to other system components such as the interface cable.
NOTE: The API provides several built-in self-tests described in the Troubleshooting Section 5.3. These
can be implemented in the application software and help diagnose and debug potential hardware
failures along the entire signal chain from ASIC to PC.
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