Linear Technology DC1705C Demo Manual page 2

DEMO MANUAL DC1705C
TYPICAL DC1705C REQUIREMENTS AND CHARACTERISTICS
PARAMETER
3.3V Power Supply
5V Power Supply
+
REF IN, Reference Frequency
REF OUT, Buffered Reference
+ –
RF and RF
Loop Bandwidth
* These frequencies are for the DC1705C pllset files included with PLLWizard.
Note 1: A low noise 10MHz or 100MHz reference frequency, such as the Wenzel 501-04608A or 501-04516D OCXO, is recommended. If using a different
frequency, make sure to update the f
used, f should be changed to 20MHz and R_DIV to 20. REF BST and FILT under the System tab in PLLWizard might need to be changed if the reference
REF
frequency and/or power is different than what is recommended in the table above. More information can be found in the LTC6946 data sheet.
Table 1. DC1705C Options and Frequency Ranges
ASSEMBLY VERSION
DC1705C-A
DC1705C-B
DC1705C-C
DC1705C-D
2
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INPUT OR OUTPUT
Input 3.3V and GND Banana Jacks
Input 5V and GND Banana Jacks
Input
Output
Two Outputs J4 and J5 SMA Connectors
– Set by Loop Filter Component Values 47kHz*
and R_DIV boxes under the System tab in PLLWizard so that f
REF
PART NUMBER VCO FREQUENCY RANGE (GHz)
LTC6946IUFD-1 2.240 to 3.740
LTC6946IUFD-2 3.080 to 4.910
LTC6946IUFD-3 3.840 to 5.790
LTC6946IUFD-4 4.200 to 6.390
PHYSICAL LOCATION DETAILS
Low Noise and Spur-Free 3.3V, 115mA
Low Noise and Spur-Free 5V, 45mA
J1 SMA Connector Low Noise 10MHz or 100MHz*, 6dBm into 50Ω
(Note 1)
J3 SMA Connector Frequency = f
Frequency: 900MHz*, Power: 0dBm, Frequency
Range: Depends on the version of the LTC6946
device – refer to Table 1, Step Size: 200kHz*
is still 1MHz. For example, if a 20MHz clock is
PFD
OUTPUT DIVIDER SETTINGS
Integers 1 through 6
Integers 1 through 6
Integers 1 through 6
Integers 1 through 6
, 0dBm
REF
dc1705cfb