Sony SIU-100 Service Manual page 82

IC
AK5383VF-E2 (AKM)
DUAL 24-BIT A/D CONVERTER
—TOP VIEW—
INPUTS
AINL+, AINL_,
1 28
AINR+, AINR_
CMODE
2 27
DFS
HPFE
3 26
MCLK
RST
4 25
SMODE1, SMODE2
TEST
5
24
ZCAL
6
23
OUTPUTS
CAL
7 22
SDATA
VCOML, VCOMR
8 21
VREFL, VREFR
9 20
INPUTS/OUTPUTS
FSYNC
10 19
LRCK
SCLK
11
18
OTHERS
12 17
A.GND
A.V
13 16
BGND
D.GND
14 15
D.V
GNDL, GNDR
PIN PIN
I/O SIGNAL I/O
NO. NO.
1 O VREFL 8 —
2 — 9
GNDL O
3 O VCOML 10 O
+
4 I AINL 11 I
_
5 I AINL 12 I
6 I ZCAL 13 I/O
7 — 14
D.V I/O
CC
* : NOTE
CMODE : AK5392
DFS : AK5393 , AK5383
12, 11
SMODE1, SMODE2
3
VCOML
∆∑
4, 5
+ _
AINL , AINL
MODULATOR
6
ZCAL
∆∑
25, 24
+ _
AINR , AINR
MODULATOR
26
VCOMR
10
RST
1, 28
VREFL, VREFR
VOLTAGE
2, 27
REFERENCE
GNDR, GNDR
4-4
: L/R CH ANALOG
: MASTER CLOCK SELECT (L: 256fs, H: 384fs)
: DOUBLE FAST SAMPLING MODE SELECT
: HPF ENABLE
: MASTER CLOCK
: RESET
: SERIAL INTERFACE MODE SELECT
: TEST
: ZERO CALIBRATION
: CALIBRATION STATUS
: SERIAL DATA
: L/R CH COMMON VOLTAGE
: L/R CH REFERENCE VOLTAGE
: FRAME SYNC CLOCK
: L/R CH SELECT CLOCK
: SERIAL DATA CLOCK
: ANALOG GROUND
: ANALOG POWER SUPPLY
CC
: BOARD GROUND
: DIGITAL POWER SUPPLY
: DIGITAL GROUND
CC
: L/R CH REFERENCE GROUND
PIN PIN
SIGNAL I/O SIGNAL
NO. NO.
D.GND 15 O SDATA 22
16 23
CAL I/O FSYNC
RST
17 I MCLK 24
18 * I * CMODE/DFS *
SMODE2 25
19 I HPFE 26
SMODE1
LRCK 20 I TEST 27
21 28
SCLK — BGND
SERIAL OUTPUT INTERFACE
DECIMATION
HPF
FILTER
DECIMATION
HPF
FILTER
CALIBRATION
CONTROLLER
SRAM
* : NOTE
CMODE
DFS
EPM7032SLC44-10(05) (ALTERA)
PROGRAMMABLE LOGIC DEVICE
—TOP VIEW—
6 5 4 3
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
PIN
I/O SIGNAL
NO.
GCLR
1 I INPUT/
OE2
2 I INPUT/
3 — V
CC
4 I/O I/O
5 I/O I/O
6 I/O I/O
7 I/O I/O (TDI)
8 I/O I/O
I/O SIGNAL 9 I/O I/O
10 — GND
—
A.GND
11 — V
CC
—
A.V
CC
_
I AINR
+
I AINR
O VCOMR
— GNDR
43
GCLK1
O VREFR
1
GCLR
44
OE1
2
OE2
4 - 9,
12 - 14,
16 - 21 I/O
CONTROL
I/O
BLOCK
16
14
SCLK
13
LRCK
16
FSYNC
15
SDATA
19
HPFE
M51954BL (MITSUBISHI)
9
CAL VOLTAGE DETECTION SYSTEM RESET
17
MCLK
—SIDE VIEW—
18
CMODE/DFS *
: AK5392
: AK5393, AK5383
1 2 3
5 uA
_
+
1.25 V
2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
12 I/O I/O 23 — V
CC
13 I/O I/O (TMS) 24 I/O I/O
14 I/O I/O 25 I/O I/O
15 — V 26 I/O I/O
CC
16 I/O I/O 27 I/O I/O
17 I/O I/O 28 I/O I/O
18 I/O I/O 29 I/O I/O
19 I/O I/O 30 — GND
20 I/O I/O 31 I/O I/O
21 I/O I/O 32 I/O I/O (TCK)
22 — GND 33 I/O I/O
MACROCELL PIA MACROCELL
(1 - 16) (17 - 32)
16 16 16
16 16
*
ABOVE DIAGRAM SHOWS CONDITIONS BEFORE PROGRAMMING
4 5
5
OUT
+
3
GND
PIN
I/O SIGNAL
NO.
34 I/O I/O
35 — V
CC
36 I/O I/O
37 I/O I/O
38 I/O I/O (TDO)
39 I/O I/O
40 I/O I/O
41 I/O I/O
42 — GND
43 I INPUT/GCLK1
OE1
44 I INPUT/
24 - 29,
31 - 34,
I/O 36 - 41
CONTROL
I/O
BLOCK
16 16
SIU-100/100T