Section 6
BP-Additions to base documentation
Table 21:
Function/ Parameter
Logic for four binary inputs with the following three
configurations:
•
OR gate
•
AND gate
•
Bistable flip-flop with two set and two reset inputs (both OR
gates), resetting takes priority
Four independent parameter sets
All configurations have an additional blocking input. Provision for inverting all inputs.
Table 22:
Function/ Parameter
Pick up or reset time
Integration
•
For delaying pick up or reset or for integrating one binary signal
•
Provision for inverting the input
•
Four independent parameter sets
Table 23:
Function/ Parameter
Pick up differential for sum of internal summation current
Amplitude compensation for summation CT
Delay
Determination of the sum and phase sequence of the three-phase currents
Four independent parameter sets
Accuracies
Accuracy of the pick up setting at rated frequency
Reset ratio
Table 24: Three phase voltage plausibility 47 (PTUV)
Function/ Parameter
Pick up differential for sum of internal summation voltage
Amplitude compensation for summation VT
Delay
Determination of the sum and phase sequence of the three-phase voltages
Four independent parameter sets
Accuracies
Accuracy of the pick up setting at rated frequency
Reset ratio
34
Logic
Delay/ integrator
Three phase current plausibility 46 (PTOC)
© 2019 - 2020 Hitachi Power Grids. All rights reserved
1MRK 505 403-UEN Rev. C
Range/ Value
Accuracy
-
-
-
-
Range/ Value
Accuracy
0 to 300 s in
-
steps of 0.01 s
yes/no
-
Range/ Value
0.05 to 1.00 I
in steps of 0.05 I
N
-2.00 to +2.00 in steps of 0.01
0.1 to 60 s in steps of 0.1 s
Value
±2% I
in the range 0.2 to 1.2 I
N
≥90% whole range
Range/ Value
0.05 to 1.2 U
in steps of 0.05 U
N
-2.00 to +2.00 in steps of 0.01
0.1 to 60 s in steps of 0.1 s
Value
±2% U
in the range 0.2 to 1.2 U
N
>95% (at U > 0.1 U
or I > 0.1 I
N
Bay protection functions REB500
N
N
N
N
)
N
Application manual